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| * heap: Remove custom bounding-box typegatecat2022-12-071-6/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-0726-57/+57
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1055 from yrabbit/pll-pinsmyrtle2022-12-065-16/+140
|\ \ | |/ |/| gowin: add PLL pins processing
| * gowin: change the way networks are handledYRabbit2022-12-061-7/+8
| | | | | | | | | | | | | | Until a comprehensive clock router is developed, the order in which private cases are handled is important. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into pll-pinsYRabbit2022-12-0413-17/+17
| |\
| * | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | Merge pull request #1056 from YosysHQ/gatecat/generic-fix-constsmyrtle2022-12-061-0/+3
|\ \ \ | |_|/ |/| | viaduct: Fix constant connectivity
| * | viaduct: Fix constant connectivitygatecat2022-12-061-0/+3
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1054 from YosysHQ/gatecat/api-add-constmyrtle2022-12-0413-17/+17
|\ \ | |/ |/| api: Make NetInfo* of checkPipAvailForNet const
| * Unbreak CIgatecat2022-12-021-5/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-0212-12/+12
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1048 from yrabbit/chipdb-cfgmyrtle2022-12-023-5/+23
|\ | | | | gowin: add information about pin configurations
| * gowin: update the apicula versionYRabbit2022-12-021-1/+1
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into chipdb-cfgYRabbit2022-12-021-2/+2
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* | Merge pull request #1053 from YosysHQ/gatecat/pbfixmyrtle2022-11-281-2/+2
|\ \ | | | | | | ecp5: Fix Python bindings for pip iterators
| * | ecp5: Fix Python bindings for pip iteratorsgatecat2022-11-281-2/+2
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: add information about pin configurationsYRabbit2022-11-252-4/+22
|/ | | | | | | Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others. This allows a decision to be made about special network routing of such pins Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1045 from yrabbit/unused-portsmyrtle2022-11-202-0/+16
|\ | | | | gowin: mark the PLL ports that are not in use
| * gowin: mark the PLL ports that are not in useYRabbit2022-11-202-0/+16
|/ | | | | | | Unused ports are deactivated by special fuse combinations, rather than being left dangling in the air. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1042 from yrabbit/add-z1myrtle2022-11-121-1/+1
|\ | | | | gowin: add support for a more common chip
| * gowin: add support for a more common chipYRabbit2022-11-121-1/+1
| | | | | | | | | | | | | | | | The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former chip is already very hard to buy, so let's experiment with a more affordable chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1040 from yrabbit/pll-stage0myrtle2022-11-116-8/+210
|\| | | | | gowin: add initial PLL support
| * gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
| | | | | | | | | | | | | | Replacing snprintf() with ctx->idf() in PLL commit, but not yet a complete overhaul. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: add initial PLL supportYRabbit2022-11-106-1/+227
| | | | | | | | | | | | | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warningmyrtle2022-11-101-0/+1
|\ \ | | | | | | Fix "implicit copy constructor for 'Property' is deprecated"
| * | Fix "implicit copy constructor for 'Property' is deprecated"gatecat2022-11-101-0/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* / fabulous: Tweak delay estimategatecat2022-11-101-0/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1037 from YosysHQ/fix_python_verMiodrag Milanović2022-10-241-1/+2
|\ | | | | Fix python version in CI
| * Fix python version in CIMiodrag Milanovic2022-10-241-1/+2
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* Update CI scriptMiodrag Milanovic2022-10-241-6/+6
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* run clangformatgatecat2022-10-172-7/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1034 from lushaylabs/support-windows-crlfmyrtle2022-10-171-4/+4
|\ | | | | Support windows line endings in constraints for nextpnr-gowin
| * support windows line endingsLushay Labs2022-10-091-4/+4
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* | Merge pull request #1035 from tyler274/patch-1myrtle2022-10-171-1/+1
|\ \ | |/ |/| Correct Not Equal operator implementation in ice40
| * Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
|/ | | I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
* Merge pull request #1032 from davidlattimore/registered-output-xformmyrtle2022-10-052-0/+9
|\ | | | | nexus: Transform registered output parameters
| * nexus: Transform registered output parametersDavid Lattimore2022-10-052-0/+9
|/ | | | | | | | | | | | Dual ported: OUTREG_A -> OUT_REGMODE_A OUTREG_B -> OUT_REGMODE_B Pseudo dual ported: OUTREG -> OUT_REGMODE_B Single ported: OUTREG -> OUT_REGMODE_A
* Merge pull request #1031 from YosysHQ/gatecat/fab-nextmyrtle2022-09-305-2/+130
|\ | | | | fabulous: Add support for the CLB muxes
| * fabulous: Pack, validity check and FASM support for muxesgatecat2022-09-304-5/+84
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * fabulous: Add split MUX belsgatecat2022-09-302-1/+50
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fixmyrtle2022-09-261-15/+21
|\ | | | | ice40: Fix handling of carry out route-thru via 25,14
| * ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1029 from airskywater/airskywater-patch-1myrtle2022-09-241-0/+6
|\ | | | | Fix runtime segmentation fault
| * Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
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| * Add more sanity check for pointersairskywater2022-09-241-0/+1
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| * fix runtime segmentation faultairskywater2022-09-241-0/+5
|/ | | disable null pointer dereference!
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-204-11/+300
|\ | | | | Support cross-domain clock relations in timing analyser
| * Added the --ignore-rel-clk option to control timing checks for cross-domain ↵Maciej Kurc2022-09-203-115/+108
| | | | | | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Code cleanupMaciej Kurc2022-08-312-68/+39
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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