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* HeAP: Add timeout to IO placementDavid Shah2020-06-251-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix typowhitequark2020-06-251-1/+1
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* Merge pull request #459 from whitequark/better-chipdbDavid Shah2020-06-2514-293/+362
|\ | | | | CMake: rewrite chipdb handling from ground up
| * CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-254-5/+4
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| * CMake: rewrite chipdb handling from ground up.whitequark2020-06-2513-288/+358
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| * CMake: only request a CXX compiler.whitequark2020-06-242-2/+2
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* | Merge pull request #458 from whitequark/patch-1David Shah2020-06-241-3/+0
|\ \ | |/ |/| Remove dead links from README
| * Remove dead links from READMEwhitequark2020-06-241-3/+0
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* Merge pull request #457 from whitequark/better-bbaDavid Shah2020-06-243-22/+30
|\ | | | | CMake: promote bba to a true subproject
| * CMake: promote bba to a true subproject.whitequark2020-06-233-22/+30
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* clangformatDavid Shah2020-06-121-12/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #454 from YosysHQ/ecp5-global-placeDavid Shah2020-06-101-2/+44
|\ | | | | ecp5: Fix placement of DCCs to guarantee routeability
| * ecp5: Fix placement of DCCs to guarantee routeabilityDavid Shah2020-06-101-2/+44
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #452 from smunaut/ice40_shiftreg_div_modeDavid Shah2020-06-021-2/+12
|\ | | | | ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
| * ice40: Add fallback behavior for Extra Cell config bits vectorsSylvain Munaut2020-06-021-1/+11
| | | | | | | | | | | | | | This helps make new nextpnr compatible with old chipdbs when a parameters goes from single bit to multi bit. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODESylvain Munaut2020-06-021-1/+1
|/ | | | | | This requires the matching chipdb update from icestorm project ! Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #447 from whitequark/wasiDavid Shah2020-05-248-20/+108
|\ | | | | Port nextpnr-{ice40,ecp5} to WASI
| * Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-238-20/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* | Merge pull request #440 from YosysHQ/lattice-fixesDavid Shah2020-05-183-0/+28
|\ \ | | | | | | Fixes for the Lattice SERDES eye demo designs
| * | ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Improve global routing robustnessDavid Shah2020-05-141-0/+11
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Don't promote VCC/GND to globals even if connected to clock portDavid Shah2020-05-141-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | lpf: Support // commentsDavid Shah2020-05-141-0/+3
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | clangformatDavid Shah2020-05-162-4/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #442 from nategraff-sifive/fix-unsupported-spellingDavid Shah2020-05-143-10/+10
|\ \ | | | | | | Fix spelling of 'unsupported'
| * | Fix spelling of 'unsupported'Nathaniel Graff2020-05-133-10/+10
| | | | | | | | | | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
* | | Merge pull request #441 from YosysHQ/eddie/fix_topoMiodrag Milanović2020-05-141-16/+16
|\ \ \ | | | | | | | | Fix embarassing use of topographical when meaning topological
| * | | Fix embarassing use of topographical when meaning topologicalEddie Hung2020-05-141-16/+16
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* | | Merge pull request #439 from edbordin/masterMiodrag Milanović2020-05-141-4/+6
|\ \ \ | |/ / |/| | Minor patch for MinGW build
| * | minor patch for MinGW buildEd Bordin2020-05-141-4/+6
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* | Merge pull request #437 from miek/lvcmos33d-driveDavid Shah2020-05-121-0/+19
|\ \ | | | | | | ecp5: Allow setting drive strength for LVCMOS33D IOs
| * | ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
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* / Add missing --top optionDavid Shah2020-05-091-0/+5
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings'David Shah2020-05-013-6/+125
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| * ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
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| * Further condenseRoss Schlaikjer2020-04-291-11/+10
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| * Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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| * Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
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| * Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
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| * Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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| * Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
|/ | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #433 from YosysHQ/dave/pyfixesDavid Shah2020-04-242-4/+17
|\ | | | | python: Miscellaneous fixes
| * python: Also convert regular map keys to stringDavid Shah2020-04-241-1/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Improve general robustness during autocompleteDavid Shah2020-04-241-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Escape strings for autocompleteDavid Shah2020-04-241-2/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Wrap map IdString key when accessed by indexDavid Shah2020-04-241-1/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #432 from smunaut/fix_disconnectDavid Shah2020-04-241-0/+1
|\ | | | | design_utils: Set port.net to null when disconnecting
| * design_utils: Set port.net to null when disconnectingSylvain Munaut2020-04-241-0/+1
|/ | | | | | | | Without this the python bindings can't actually connect anything else to a disconnected port since the assert in connect_ports will think it's still connected Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #428 from mmicko/masterMiodrag Milanović2020-04-201-2/+2
|\ | | | | Better Boost support
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