Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ice40: Add python binding for write_bitstream | gatecat | 2023-02-28 | 1 | -0/+14 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | fabulous: Add timing model for carries | gatecat | 2023-02-27 | 1 | -0/+20 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | fabulous: LUT permutation support | gatecat | 2023-02-27 | 4 | -2/+102 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | fabulous: Global constant wires scheme | gatecat | 2023-02-23 | 6 | -15/+140 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | CMake: detect platform support for threads | Catherine | 2023-02-23 | 1 | -14/+13 |
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* | common: disable parallel refinement only without threads. | Catherine | 2023-02-23 | 5 | -9/+9 |
| | | | | Previously it was always disabled on WebAssembly builds. | ||||
* | common: update deprecated use of `boost::filesystem::basename`. | Catherine | 2023-02-23 | 1 | -2/+2 |
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* | CMake: check if warning flag is supported before use. | Catherine | 2023-02-23 | 1 | -1/+9 |
| | | | | Clang 11 is failing on -Wno-format-truncation. | ||||
* | Merge pull request #1108 from whitequark/fix-includes | Catherine | 2023-02-23 | 2 | -0/+3 |
|\ | | | | | common: add missing includes for libc++ | ||||
| * | common: add missing includes for libc++. | Catherine | 2023-02-23 | 2 | -0/+3 |
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* | Merge pull request #1106 from YosysHQ/gatecat/fab_carry | myrtle | 2023-02-21 | 3 | -10/+122 |
|\ | | | | | fabulous: Add support for packing carry chains | ||||
| * | fabulous: Add support for packing carry chains | gatecat | 2023-02-21 | 3 | -10/+122 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1103 from rodgert/master | myrtle | 2023-02-21 | 1 | -0/+1 |
|\ | | | | | Include <cstdint> in common/kernel/hashlib.h | ||||
| * | Include <cstdint> in common/kernel/hashlib.h | Thomas W Rodgers | 2023-02-18 | 1 | -0/+1 |
| | | | | | | | | | | | | | | The definitions for uint32_t, uint64_t report as undefined when compiling under GCC13. They were previously found by transitive includes, but this is not guaranteed to work, and GCC13 forced the issue. | ||||
* | | Merge pull request #1105 from YosysHQ/gatecat/nexus-io-error | myrtle | 2023-02-21 | 1 | -0/+10 |
|\ \ | |/ |/| | nexus: Check IO-bank compatibility | ||||
| * | nexus: Check IO-bank compatibility | gatecat | 2023-02-21 | 1 | -0/+10 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | fabulous: Further tweak magic numbers | gatecat | 2023-02-16 | 1 | -3/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1102 from rowanG077/print-random-seed | myrtle | 2023-02-16 | 1 | -1/+3 |
|\ | | | | | common: Print out generated seed value | ||||
| * | common: Print out generated seed value | rowanG077 | 2023-02-16 | 1 | -1/+3 |
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* | | Merge pull request #1101 from YosysHQ/gatecat/fab-fake-timings | myrtle | 2023-02-16 | 2 | -6/+46 |
|\ \ | |/ |/| | fabulous: Add fake timings | ||||
| * | fabulous: Add fake timings | gatecat | 2023-02-16 | 2 | -6/+46 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1092 from rowanG077/werror | myrtle | 2023-02-14 | 3 | -9/+29 |
|\ | | | | | common: Implement Werror flag | ||||
| * | common: Implement Werror flag | rowanG077 | 2023-02-13 | 3 | -9/+29 |
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* | | Update links to IceStorm in README | Catherine | 2023-02-14 | 1 | -3/+3 |
| | | | | | | Fixes #1099. | ||||
* | | Merge pull request #1098 from YosysHQ/lofty/fix-machxo2-pybindings | myrtle | 2023-02-13 | 1 | -2/+2 |
|\ \ | | | | | | | machxo2: Fix Python bindings for pip iterators | ||||
| * | | machxo2: Fix Python bindings for pip iterators | Lofty | 2023-02-13 | 1 | -2/+2 |
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* | | Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ct | myrtle | 2023-02-13 | 2 | -14/+160 |
|\ \ | | | | | | | ecp5: Propagate clock constraints through DCSC | ||||
| * | | streamline constant_net detection | rowanG077 | 2023-02-06 | 2 | -4/+8 |
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| * | | ecp5: DSCS clock propagation if modesel is 0 constant | rowanG077 | 2023-02-06 | 1 | -52/+99 |
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| * | | ecp5: Propagate clock constraints through DSCS | rowanG077 | 2023-02-01 | 1 | -12/+107 |
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* | | Merge pull request #1097 from YosysHQ/gatecat/fab-bram-fix | myrtle | 2023-02-10 | 2 | -6/+25 |
|\ \ | | | | | | | fabulous: Improve names for BRAM bels | ||||
| * | | fabulous: Improve names for BRAM bels | gatecat | 2023-02-10 | 2 | -6/+25 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #1096 from YosysHQ/gatecat/ecp5-ioce-fix | myrtle | 2023-02-10 | 1 | -2/+8 |
|\ \ | | | | | | | ecp5: Handle the case where both CE are the same constant | ||||
| * | | ecp5: Handle the case where both CE are the same constant | gatecat | 2023-02-09 | 1 | -2/+8 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #1094 from uis246/master | myrtle | 2023-02-07 | 2 | -0/+21 |
|\ \ | | | | | | | gowin: Add bels for new types of oscillators | ||||
| * | | gowin: Add bels for new types of oscillator | uis | 2023-02-06 | 2 | -0/+21 |
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* | | Merge pull request #1087 from yrabbit/gw1nr-9 | myrtle | 2023-02-02 | 3 | -46/+65 |
|\ \ | | | | | | | gowin: Add PLL support for the GW1NR-9 chip | ||||
| * \ | Merge branch 'master' into gw1nr-9 | YRabbit | 2023-02-02 | 4 | -24/+52 |
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* | | | Merge pull request #1089 from smunaut/icegate | myrtle | 2023-02-01 | 3 | -14/+24 |
|\ \ \ | | | | | | | | | ice40: Add support for PLL ICEGATE function | ||||
| * | | | ice40: Don't assert on unknown extra_config bits if they are 0 | Sylvain Munaut | 2023-02-01 | 1 | -1/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bits are 0 by default anyway, so if they are unknown (because icestorm is too od) but we want them at 0 ... it's not much of an issue. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | | ice40: Add support for PLL ICEGATE function | Sylvain Munaut | 2023-02-01 | 3 | -13/+19 |
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | Technically you can enable it independently on CORE and GLOBAL output, but this is not exposed in the classic primitive, so we do the same as icecube2 and enable/disable it for both output path depending on the argument Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | | Merge pull request #1088 from rowanG077/ecp5-singleton-lpf | myrtle | 2023-01-31 | 1 | -1/+8 |
|\ \ \ | |_|/ |/| | | ecp5: LOCATE in LPF works on singleton vector | ||||
| * | | ecp5: LOCATE in LPF works on singleton vector | rowanG077 | 2023-01-31 | 1 | -1/+8 |
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* | | Merge pull request #1086 from smunaut/out_z | myrtle | 2023-01-30 | 1 | -9/+20 |
|\ \ | | | | | | | ice40: Improve `output` handling vs pull-ups and undriven | ||||
| * | | ice40: Support for undriven / unconnected output ports | Sylvain Munaut | 2023-01-29 | 1 | -1/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | If a port specified as output (and thus had a $nextpnr_obuf inserted) is undriven (const `z` or const `x`), we make sure to not enable the output driver. Also enable pull-ups if it was requested by the user. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | ice40: Rework pull-up attribute copy to SB_IO blocks | Sylvain Munaut | 2023-01-29 | 1 | -8/+14 |
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We try to copy the attribute only when there is a chance for the output driver to not be active. Note that this can _also_ happen when a port is specified as output but has a TBUF, which the previous code wasn't handling. We could copy the attribute "all-the-time" but this would mean if a user specified a `-pullup yes` in the PCF for a permanently driven output pin, we'd be burning power for nothing. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | gowin: Add PLL support for the GW1NS-2C chip | YRabbit | 2023-01-31 | 2 | -1/+8 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: Add PLL support for GW1NR-4 chips | YRabbit | 2023-01-31 | 2 | -2/+6 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: Proper use of the C++ mechanisms | YRabbit | 2023-01-30 | 2 | -10/+8 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: Add PLL support for the GW1NR-9 chip | YRabbit | 2023-01-30 | 3 | -46/+56 |
|/ | | | | | | | | | And also unified the fixing of PLL to bels: the point is that PLL being at a certain location has the possibility to use a direct implicit wire to the clock source, but once we decide to use this direct wire, the PLL can no longer be moved. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |