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* ecp5: Flatten bel_to_cell for performanceDavid Shah2018-08-182-23/+21
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Speed up Bel availability/binding checksDavid Shah2018-08-181-5/+11
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Speedup placement using ArchCellInfoDavid Shah2018-08-184-12/+42
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Speedup router with slightly better estimatesDavid Shah2018-08-181-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
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* Added ability for static buildsMiodrag Milanovic2018-08-162-1/+15
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* Merge pull request #48 from YosysHQ/placer_speedupEddie Hung2018-08-114-32/+66
|\ | | | | placer: low hanging speedups
| * Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-1012-36/+116
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* | Fix compile warningMiodrag Milanovic2018-08-091-0/+2
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* | Expose log_always that will be displayed disregarding quite flagMiodrag Milanovic2018-08-092-12/+10
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* | Added quiet mode for loggingMiodrag Milanovic2018-08-093-15/+28
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* | Fix MSVC compileMiodrag Milanovic2018-08-091-0/+1
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* | Merge pull request #42 from YosysHQ/floorplanDavid Shah2018-08-098-20/+86
|\ \ | | | | | | Add basic data structures for floorplanning
| * | ecp5: Implement getPipLocation and related APIDavid Shah2018-08-091-1/+11
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | Add pip locationsClifford Wolf2018-08-097-19/+61
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add Region structClifford Wolf2018-08-091-0/+14
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵Eddie Hung2018-08-103-17/+18
| | | | | | | | | | | | std::array
| | * std::vector::resize() not reserve()Eddie Hung2018-08-091-1/+1
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| | * Make containers staticEddie Hung2018-08-091-5/+7
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| | * Get rid of map lookup by borrowing udata to use as index into vectorEddie Hung2018-08-091-19/+20
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| | * Try with vectorEddie Hung2018-08-091-17/+47
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* | ice40: Speedup Arch::predictDelay() with pass-by-refEddie Hung2018-08-081-1/+1
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* | Make loading works nice and use settingsMiodrag Milanovic2018-08-087-30/+36
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* | Merge pull request #46 from YosysHQ/use_settingsMiodrag Milanović2018-08-0811-27/+68
|\ \ | |/ |/| Use settings for json and pcf
| * Use settings for json and pcfMiodrag Milanovic2018-08-0811-27/+68
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* Merge pull request #45 from YosysHQ/constidsClifford Wolf2018-08-0831-553/+285
|\ | | | | Get rid of PortPin and BelType
| * Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-0829-913/+1270
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* | Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-0810-140/+374
|\ \ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| * | ice40: Add error for unknown cell type when getting timing infoDavid Shah2018-08-081-1/+3
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | docs: Update Arch API Cell Timing docsDavid Shah2018-08-081-6/+4
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | timing: Remove unused variableDavid Shah2018-08-081-1/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | timing: Update to use getDelayNSDavid Shah2018-08-081-11/+14
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | One more breadcrumbEddie Hung2018-08-081-0/+1
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| * | Leave comment behind about removing false pathsEddie Hung2018-08-081-1/+1
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| * | clangformatDavid Shah2018-08-081-6/+12
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | Arch API: Removing Arch::isIOCellDavid Shah2018-08-085-10/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | Unfurl comments for clangformatEddie Hung2018-08-081-28/+12
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| * | Disable assign_budget() after placement legalisation, unless slack redistEddie Hung2018-08-081-1/+4
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| * | Merge branch 'master' into improve_timing_specEddie Hung2018-08-081-0/+12
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| * | | Also include TMG_GEN_CLOCK as a timing startpointEddie Hung2018-08-081-3/+2
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| * | | ice40: Add timing arcs through global buffersDavid Shah2018-08-081-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | timing: Debugging implementation of new timing APIDavid Shah2018-08-082-5/+10
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | ice40: Timing arch fixDavid Shah2018-08-081-3/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | timing: Update to new use API (currently broken)David Shah2018-08-085-19/+33
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | Arch API: New specification for timing port classesDavid Shah2018-08-087-35/+66
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | common: Add TimingPortClassDavid Shah2018-08-081-1/+14
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | Cleanup nestingEddie Hung2018-08-061-59/+59
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| * | | Do less work if update flag is falseEddie Hung2018-08-061-6/+6
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| * | | clangformatEddie Hung2018-08-064-51/+57
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| * | | Also add PLL outputs as timing startpointsEddie Hung2018-08-061-15/+3
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