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* Fix spelling of 'unsupported'Nathaniel Graff2020-05-133-10/+10
| | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
* Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings'David Shah2020-05-013-6/+125
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| * ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
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| * Further condenseRoss Schlaikjer2020-04-291-11/+10
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| * Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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| * Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
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| * Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
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| * Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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| * Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
|/ | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #433 from YosysHQ/dave/pyfixesDavid Shah2020-04-242-4/+17
|\ | | | | python: Miscellaneous fixes
| * python: Also convert regular map keys to stringDavid Shah2020-04-241-1/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Improve general robustness during autocompleteDavid Shah2020-04-241-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Escape strings for autocompleteDavid Shah2020-04-241-2/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * python: Wrap map IdString key when accessed by indexDavid Shah2020-04-241-1/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #432 from smunaut/fix_disconnectDavid Shah2020-04-241-0/+1
|\ | | | | design_utils: Set port.net to null when disconnecting
| * design_utils: Set port.net to null when disconnectingSylvain Munaut2020-04-241-0/+1
|/ | | | | | | | Without this the python bindings can't actually connect anything else to a disconnected port since the assert in connect_ports will think it's still connected Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #428 from mmicko/masterMiodrag Milanović2020-04-201-2/+2
|\ | | | | Better Boost support
| * old boost supportMiodrag Milanovic2020-04-201-2/+2
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* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #426 from YosysHQ/dave/fix-pll2eclkDavid Shah2020-04-151-1/+80
|\ | | | | ecp5: Use dedicated routing for ECLKs where possible
| * ecp5: Use dedicated routing for ECLKs where possibleDavid Shah2020-04-141-1/+80
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Add TRELLIS_PROGRAM_PREFIXMiodrag Milanovic2020-04-111-4/+6
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* Merge pull request #424 from mmicko/program_prefixDavid Shah2020-04-101-10/+12
|\ | | | | Support custom PROGRAM_PREFIX
| * Support custom PROGRAM_PREFIXMiodrag Milanovic2020-04-101-10/+12
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* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-073-4/+33
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
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| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
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| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
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| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-073-19/+23
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-073-8/+16
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| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
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* | Merge pull request #419 from garytwong/handle-opendrainDavid Shah2020-04-071-0/+3
|\ \ | | | | | | Handle OPENDRAIN attribute.
| * | Handle OPENDRAIN attribute.Gary Wong2020-04-031-0/+3
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* | | Merge pull request #421 from garytwong/fix-lpf-locate-assertion-failureDavid Shah2020-04-071-0/+2
|\ \ \ | | | | | | | | Fix assertion failure on invalid LOCATE input.
| * | | Fix assertion failure on invalid LOCATE input.Gary Wong2020-04-051-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to parse this invalid LPF syntax: LOCATE COMP "a" SITE "A1" IOBUF PORT "a" IO_TYPE=LVCMOS33; (note missing semicolon on first line) gives an assertion failure in strip_quotes, because the fifth token is scanned as "A1"IOBUF (without a trailing quote). Avoid the problem by detecting extraneous input and issuing a more specific error.
* | | Merge pull request #420 from ironsteel/fix-reporting-of-default-routerDavid Shah2020-04-041-1/+1
|\ \ \ | |/ / |/| | command.cc: Use correct constant for default router
| * | command.cc: Use correct constant for default routerRangel Ivanov2020-04-041-1/+1
| | | | | | | | | | | | | | | | | | Otherwise --help reports that the default router is heap Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
* | | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pinDavid Shah2020-04-031-0/+10
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #418 from garytwong/usrmclk-worksDavid Shah2020-04-031-1/+1
|\ \ \ | | | | | | | | Remove comment about the USRMCLK primitive being untested.
| * | | Remove comment about the USRMCLK primitive being untested.Gary Wong2020-04-021-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested and verified working: the trivial configuration: module USRMCLK( USRMCLKI, USRMCLKTS ); input USRMCLKI, USRMCLKTS; endmodule module top( input clk ); reg[ 24:0 ] count = 0; always @( posedge clk ) begin count <= count + 1'b1; end USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) ); endmodule produces the expected output (toggling at high frequency, toggling tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate clock. See https://bayimg.com/AAnNKAAGO for an example. The top (magenta) trace is the MCLK line.
* | | Merge pull request #417 from hackfin/masterDavid Shah2020-04-021-2/+7
|\ \ \ | |/ / |/| | Enum/int compatibility for EHXPLLL parameters
| * | Enum/int compatibility for EHXPLLL parametersMartin2020-04-021-2/+7
|/ / | | | | | | | | | | - Lattice component EHXPLLL parameter compatibility, allowing to pass an int parameter for the enum (as expected by trellis tile) e.g. CLKOP_TRIM_DELAY : integer := 0;
* | ice40: Derive oscillator frequency constraintsDavid Shah2020-03-291-0/+40
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #415 from smunaut/fix_iob_oe_regDavid Shah2020-03-291-1/+1
|\ \ | | | | | | ice40: Fix output register timing analysis for registered output enable
| * | ice40: Fix output register timing analysis for registered output enableSylvain Munaut2020-03-291-1/+1
|/ / | | | | | | | | | | | | Wrong bits were being tested. [5:4] is what's controlling the output enable path. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #410 from YosysHQ/ecp5-12kDavid Shah2020-03-254-7/+21
|\ \ | | | | | | ecp5: Proper support for '12k' device
| * | ecp5: Proper support for '12k' deviceDavid Shah2020-03-134-7/+21
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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