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Author
Age
Files
Lines
*
ci: Bump mistral version
gatecat
2021-06-05
1
-1
/
+1
*
Remove redundant code after hashlib move
gatecat
2021-06-02
1
-1
/
+1
*
interchange: Add LIFCL-40 EVN tests
gatecat
2021-06-01
1
-1
/
+1
*
ci: Use GH only for Mistral and fpga-interchange
gatecat
2021-05-15
1
-0
/
+24
*
ci: Re-enable abseil for interchange CI
gatecat
2021-04-14
1
-1
/
+1
*
interchange: Pin prjoxide commit
gatecat
2021-04-09
1
-0
/
+2
*
[interchange] Update interchange CI for new chipdb change.
Keith Rothman
2021-04-01
1
-1
/
+1
*
interchange: Fix nexus cmake review comments
gatecat
2021-03-31
1
-7
/
+7
*
ci: Build prjoxide only for LIFCL
gatecat
2021-03-30
1
-6
/
+7
*
interchange: Add Nexus to CI
gatecat
2021-03-30
1
-0
/
+8
*
gh-actions: better yosys caching based on version
Alessandro Comodi
2021-03-26
1
-2
/
+2
*
gh-actions: use ccache and build tools before running tests
Alessandro Comodi
2021-03-25
1
-39
/
+43
*
gh-actions: interchange: multiple jobs, one for each device
Alessandro Comodi
2021-03-24
1
-2
/
+2
*
[FPGA interchange] Add support for global buffers from chipdb.
Keith Rothman
2021-03-23
1
-1
/
+1
*
Use new parameter definition data in FPGA interchange processing.
Keith Rothman
2021-03-23
1
-1
/
+1
*
Increment required python-fpga-interchange version.
Keith Rothman
2021-03-22
1
-1
/
+1
*
github-actions: use capnp v0.8.0
Alessandro Comodi
2021-03-16
1
-3
/
+3
*
github-actions: pin python-fpga-interchange to tag
Alessandro Comodi
2021-03-16
1
-1
/
+2
*
github-actions: add basic CI to test FPGA interchange
Alessandro Comodi
2021-03-16
1
-0
/
+47