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-rw-r--r--ice40/arch.cc1
-rw-r--r--ice40/arch.h2
-rw-r--r--ice40/arch_place.cc4
-rw-r--r--ice40/bitstream.cc5
-rw-r--r--ice40/chains.cc3
-rw-r--r--ice40/delay.cc2
-rw-r--r--ice40/gfx.cc7
-rw-r--r--ice40/pack.cc38
8 files changed, 34 insertions, 28 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 43a3dec2..f008b617 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -414,7 +414,6 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
return ret;
}
-
// -----------------------------------------------------------------------
BelId Arch::getPackagePinBel(const std::string &pin) const
diff --git a/ice40/arch.h b/ice40/arch.h
index 37f663d9..27d5db9f 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -817,7 +817,7 @@ struct Arch : BaseCtx
bool isBelLocationValid(BelId bel) const;
// Helper function for above
- bool logicCellsCompatible(const CellInfo** it, const size_t size) const;
+ bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
// -------------------------------------------------
// Assign architecure-specific arguments to nets and cells, which must be
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index b436f7d7..c97b9c26 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -27,13 +27,13 @@
NEXTPNR_NAMESPACE_BEGIN
-bool Arch::logicCellsCompatible(const CellInfo** it, const size_t size) const
+bool Arch::logicCellsCompatible(const CellInfo **it, const size_t size) const
{
bool dffs_exist = false, dffs_neg = false;
const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
int locals_count = 0;
- for (auto cell : boost::make_iterator_range(it, it+size)) {
+ for (auto cell : boost::make_iterator_range(it, it + size)) {
NPNR_ASSERT(cell->type == id_ICESTORM_LC);
if (cell->lcInfo.dffEnable) {
if (!dffs_exist) {
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 124be092..e56ed37d 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -472,7 +472,6 @@ void write_asc(const Context *ctx, std::ostream &out)
}
}
-
if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), !input_en);
set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
@@ -512,8 +511,6 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(ciey).at(ciex), "IoCtrl.cf_bit_35", !pullup);
}
}
-
-
}
} else if (cell.second->type == ctx->id("SB_GB")) {
// no cell config bits
@@ -914,7 +911,7 @@ bool read_asc(Context *ctx, std::istream &in)
}
if (isUsed) {
NetInfo *net = ctx->wire_to_net[pi.dst];
- if (net!=nullptr) {
+ if (net != nullptr) {
WireId wire;
wire.index = pi.dst;
ctx->unbindWire(wire);
diff --git a/ice40/chains.cc b/ice40/chains.cc
index bb20b60b..e8a7ab17 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -97,7 +97,8 @@ class ChainConstrainer
}
tile.push_back(cell);
chains.back().cells.push_back(cell);
- bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) || (int(chains.back().cells.size()) > max_length);
+ bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) ||
+ (int(chains.back().cells.size()) > max_length);
if (split_chain) {
CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")));
tile.pop_back();
diff --git a/ice40/delay.cc b/ice40/delay.cc
index d76aaefb..54905551 100644
--- a/ice40/delay.cc
+++ b/ice40/delay.cc
@@ -121,7 +121,7 @@ struct model_params_t
int delta_sp4;
int delta_sp12;
- static const model_params_t &get(const ArchArgs& args)
+ static const model_params_t &get(const ArchArgs &args)
{
static const model_params_t model_hx8k = {588, 129253, 8658, 118333, 23915, -73105, 57696,
-86797, 89, 3706, -316, -575, -158, -296};
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index 74338b8d..320081c5 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -21,7 +21,8 @@
NEXTPNR_NAMESPACE_BEGIN
-void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, GfxTileWireId id, GraphicElement::style_t style)
+void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, GfxTileWireId id,
+ GraphicElement::style_t style)
{
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
@@ -462,7 +463,7 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, Gfx
g.push_back(el);
}
- if (idx <= 15 && (x == 0 || x == w-1) && y == 1) {
+ if (idx <= 15 && (x == 0 || x == w - 1) && y == 1) {
float y1 = y - (0.03 + 0.0025 * (60 - idx - 4));
el.x1 = x2;
@@ -478,7 +479,7 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, Gfx
g.push_back(el);
}
- if (idx >= 4 && (x == 0 || x == w-1) && y == h-2) {
+ if (idx >= 4 && (x == 0 || x == w - 1) && y == h - 2) {
float y1 = y + 2.0 - (0.03 + 0.0025 * (60 - idx));
el.x1 = x1;
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 07c003d1..35503298 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -735,11 +735,13 @@ static void pack_special(Context *ctx)
pllout_a_used++;
}
- if (pllout_a_used > 1)
- log_error("PLL '%s' is using multiple ports mapping to PLLOUT_A output of the PLL\n", ci->name.c_str(ctx));
+ if (pllout_a_used > 1)
+ log_error("PLL '%s' is using multiple ports mapping to PLLOUT_A output of the PLL\n",
+ ci->name.c_str(ctx));
- if (pllout_b_used > 1)
- log_error("PLL '%s' is using multiple ports mapping to PLLOUT_B output of the PLL\n", ci->name.c_str(ctx));
+ if (pllout_b_used > 1)
+ log_error("PLL '%s' is using multiple ports mapping to PLLOUT_B output of the PLL\n",
+ ci->name.c_str(ctx));
for (auto port : ci->ports) {
PortInfo &pi = port.second;
@@ -754,16 +756,18 @@ static void pack_special(Context *ctx)
newname = "PLLOUT_B";
if (pi.name == ctx->id("PLLOUTCORE"))
newname = "PLLOUT_A";
- if (pi.name == ctx->id("PLLOUTGLOBALA"))
+ if (pi.name == ctx->id("PLLOUTGLOBALA"))
newname = "PLLOUT_A";
if (pi.name == ctx->id("PLLOUTGLOBALB"))
newname = "PLLOUT_B";
if (pi.name == ctx->id("PLLOUTGLOBAL"))
newname = "PLLOUT_A";
-
- if (pi.name == ctx->id("PLLOUTGLOBALA") || pi.name == ctx->id("PLLOUTGLOBALB") || pi.name == ctx->id("PLLOUTGLOBAL"))
+
+ if (pi.name == ctx->id("PLLOUTGLOBALA") || pi.name == ctx->id("PLLOUTGLOBALB") ||
+ pi.name == ctx->id("PLLOUTGLOBAL"))
log_warning("PLL '%s' is using port %s but implementation does not actually "
- "use the global clock output of the PLL\n", ci->name.c_str(ctx), pi.name.str(ctx).c_str());
+ "use the global clock output of the PLL\n",
+ ci->name.c_str(ctx), pi.name.str(ctx).c_str());
if (pi.name == ctx->id("PACKAGEPIN")) {
if (!is_pad) {
@@ -782,13 +786,16 @@ static void pack_special(Context *ctx)
if (packed->ports.count(ctx->id(newname)) == 0) {
if (ci->ports[pi.name].net == nullptr) {
- log_warning("PLL '%s' has unknown unconnected port '%s' - ignoring\n", ci->name.c_str(ctx), pi.name.c_str(ctx));
+ log_warning("PLL '%s' has unknown unconnected port '%s' - ignoring\n", ci->name.c_str(ctx),
+ pi.name.c_str(ctx));
continue;
} else {
if (ctx->force) {
- log_error("PLL '%s' has unknown connected port '%s'\n", ci->name.c_str(ctx), pi.name.c_str(ctx));
+ log_error("PLL '%s' has unknown connected port '%s'\n", ci->name.c_str(ctx),
+ pi.name.c_str(ctx));
} else {
- log_warning("PLL '%s' has unknown connected port '%s' - ignoring\n", ci->name.c_str(ctx), pi.name.c_str(ctx));
+ log_warning("PLL '%s' has unknown connected port '%s' - ignoring\n", ci->name.c_str(ctx),
+ pi.name.c_str(ctx));
continue;
}
}
@@ -840,13 +847,15 @@ static void pack_special(Context *ctx)
packagepin_cell->ports.erase(pll_packagepin_driver.port);
}
- log_info(" constrained PLL '%s' to %s\n", packed->name.c_str(ctx), ctx->getBelName(bel).c_str(ctx));
+ log_info(" constrained PLL '%s' to %s\n", packed->name.c_str(ctx),
+ ctx->getBelName(bel).c_str(ctx));
packed->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
pll_bel = bel;
constrained = true;
}
if (!constrained) {
- log_error("Could not constrain PLL '%s' to any PLL Bel (too many PLLs?)\n", packed->name.c_str(ctx));
+ log_error("Could not constrain PLL '%s' to any PLL Bel (too many PLLs?)\n",
+ packed->name.c_str(ctx));
}
}
@@ -865,8 +874,7 @@ static void pack_special(Context *ctx)
// If we have a net connected to LOCK, make sure it only drives LUTs.
auto port = packed->ports[ctx->id("LOCK")];
if (port.net != nullptr) {
- log_info(" PLL '%s' has LOCK output, need to pass all outputs via LUT\n",
- ci->name.c_str(ctx));
+ log_info(" PLL '%s' has LOCK output, need to pass all outputs via LUT\n", ci->name.c_str(ctx));
bool found_lut = false;
bool all_luts = true;
unsigned int lut_count = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 06:33:22 +0000