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-rw-r--r--ice40/arch.cc37
-rw-r--r--ice40/arch.h3
-rw-r--r--ice40/bitstream.cc5
-rw-r--r--ice40/main.cc10
-rw-r--r--ice40/pack.cc12
-rw-r--r--ice40/place_legaliser.cc17
6 files changed, 45 insertions, 39 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 5ec0a42d..daf0c78b 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -188,6 +188,13 @@ Arch::Arch(ArchArgs args) : args(args)
id_i3 = id("I3");
id_dff_en = id("DFF_ENABLE");
id_neg_clk = id("NEG_CLK");
+ id_cin = id("CIN");
+ id_cout = id("COUT");
+ id_o = id("O");
+ id_lo = id("LO");
+ id_icestorm_ram = id("ICESTORM_RAM");
+ id_rclk = id("RCLK");
+ id_wclk = id("WCLK");
}
// -----------------------------------------------------------------------
@@ -702,26 +709,26 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
{
- if (cell->type == id("ICESTORM_LC")) {
- if ((fromPort == id("I0") || fromPort == id("I1") || fromPort == id("I2") || fromPort == id("I3")) &&
- (toPort == id("O") || toPort == id("LO"))) {
+ if (cell->type == id_icestorm_lc) {
+ if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
+ (toPort == id_o || toPort == id_lo)) {
delay = 450;
return true;
- } else if (fromPort == id("CIN") && toPort == id("COUT")) {
+ } else if (fromPort == id_cin && toPort == id_cout) {
delay = 120;
return true;
- } else if (fromPort == id("I1") && toPort == id("COUT")) {
+ } else if (fromPort == id_i1 && toPort == id_cout) {
delay = 260;
return true;
- } else if (fromPort == id("I2") && toPort == id("COUT")) {
+ } else if (fromPort == id_i2 && toPort == id_cout) {
delay = 230;
return true;
- } else if (fromPort == id("CLK") && toPort == id("O")) {
+ } else if (fromPort == id_clk && toPort == id_o) {
delay = 540;
return true;
}
- } else if (cell->type == id("ICESTORM_RAM")) {
- if (fromPort == id("RCLK")) {
+ } else if (cell->type == id_icestorm_ram) {
+ if (fromPort == id_rclk) {
delay = 2140;
return true;
}
@@ -731,14 +738,14 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
- if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
- if (port != id("LO") && port != id("CIN") && port != id("COUT"))
- return id("CLK");
- } else if (cell->type == id("ICESTORM_RAM")) {
+ if (cell->type == id_icestorm_lc && cell->lcInfo.dffEnable) {
+ if (port != id_lo && port != id_cin && port != id_cout)
+ return id_clk;
+ } else if (cell->type == id_icestorm_ram) {
if (port.str(this)[0] == 'R')
- return id("RCLK");
+ return id_rclk;
else
- return id("WCLK");
+ return id_wclk;
}
return IdString();
}
diff --git a/ice40/arch.h b/ice40/arch.h
index bdd43901..a9392f6d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -740,6 +740,9 @@ struct Arch : BaseCtx
IdString id_cen, id_clk, id_sr;
IdString id_i0, id_i1, id_i2, id_i3;
IdString id_dff_en, id_neg_clk;
+ IdString id_cin, id_cout;
+ IdString id_o, id_lo;
+ IdString id_icestorm_ram, id_rclk, id_wclk;
// -------------------------------------------------
BelPin getIOBSharingPLLPin(BelId pll, PortPin pll_pin) const
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index e9851a83..af5febce 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -566,9 +566,8 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(y).at(x),
"Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
else
- set_config(ti, config.at(y).at(x),
- "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
- std::to_string(lc_idx) + "_inmux02_5",
+ set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) +
+ "_LC0" + std::to_string(lc_idx) + "_inmux02_5",
true);
}
}
diff --git a/ice40/main.cc b/ice40/main.cc
index a893921b..5b658288 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -144,18 +144,16 @@ int main(int argc, char *argv[])
#endif
if (vm.count("help") || argc == 1) {
help:
- std::cout << boost::filesystem::basename(argv[0])
- << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
std::cout << "\n";
std::cout << options << "\n";
return argc != 1;
}
if (vm.count("version")) {
- std::cout << boost::filesystem::basename(argv[0])
- << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
return 1;
}
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 91dcf846..8182eb70 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -662,12 +662,12 @@ static void pack_special(Context *ctx)
auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")];
packed->params[ctx->id("FEEDBACK_PATH")] =
- feedback_path == "DELAY"
- ? "0"
- : feedback_path == "SIMPLE" ? "1"
- : feedback_path == "PHASE_AND_DELAY"
- ? "2"
- : feedback_path == "EXTERNAL" ? "6" : feedback_path;
+ feedback_path == "DELAY" ? "0" : feedback_path == "SIMPLE"
+ ? "1"
+ : feedback_path == "PHASE_AND_DELAY"
+ ? "2"
+ : feedback_path == "EXTERNAL" ? "6"
+ : feedback_path;
packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci));
NetInfo *pad_packagepin_net = nullptr;
diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc
index ebc2b865..9fde179d 100644
--- a/ice40/place_legaliser.cc
+++ b/ice40/place_legaliser.cc
@@ -90,21 +90,20 @@ static int get_cell_evilness(const Context *ctx, const CellInfo *cell)
// This returns how "evil" a logic cell is, and thus how likely it is to be ripped up
// during logic tile legalisation
int score = 0;
- if (get_net_or_empty(cell, ctx->id("I0")))
+ if (get_net_or_empty(cell, ctx->id_i0))
++score;
- if (get_net_or_empty(cell, ctx->id("I1")))
+ if (get_net_or_empty(cell, ctx->id_i1))
++score;
- if (get_net_or_empty(cell, ctx->id("I2")))
+ if (get_net_or_empty(cell, ctx->id_i2))
++score;
- if (get_net_or_empty(cell, ctx->id("I3")))
+ if (get_net_or_empty(cell, ctx->id_i3))
++score;
- if (bool_or_default(cell->params, ctx->id("DFF_ENABLE"))) {
- const NetInfo *cen = get_net_or_empty(cell, ctx->id("CEN")), *sr = get_net_or_empty(cell, ctx->id("SR"));
- if (cen)
+ if (cell->lcInfo.dffEnable) {
+ if (cell->lcInfo.cen)
score += 10;
- if (sr)
+ if (cell->lcInfo.sr)
score += 10;
- if (bool_or_default(cell->params, ctx->id("NEG_CLK")))
+ if (cell->lcInfo.negClk)
score += 5;
}
return score;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 01:26:13 +0000