diff options
Diffstat (limited to 'ice40/carry_tests/test.sh')
| -rwxr-xr-x | ice40/carry_tests/test.sh | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/ice40/carry_tests/test.sh b/ice40/carry_tests/test.sh index 9f6b00b2..01aa4209 100755 --- a/ice40/carry_tests/test.sh +++ b/ice40/carry_tests/test.sh @@ -2,15 +2,8 @@ set -ex NAME=${1%.v} yosys -p "synth_ice40 -top top; write_json ${NAME}.json" $1 -../../nextpnr-ice40 --force --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose ../../python/dump_design.py -#icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v +../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose +icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v +iverilog -o ${NAME}_sim.out ${NAME}_tb.v ${NAME}_out.v +vvp ${NAME}_sim.out -#yosys -p "read_verilog +/ice40/cells_sim.v;\ -# rename chip gate;\ -# read_verilog $1;\ -# rename top gold;\ -# hierarchy;\ -# proc;\ -# clk2fflogic;\ -# miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\ -# sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v |