diff options
Diffstat (limited to 'ice40/arch.h')
| -rw-r--r-- | ice40/arch.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 62a637ae..561d75c3 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -400,10 +400,10 @@ struct Arch : BaseCtx mutable std::unordered_map<Loc, int> bel_by_loc; std::vector<bool> bel_carry; - std::vector<CellInfo*> bel_to_cell; - std::vector<NetInfo*> wire_to_net; - std::vector<NetInfo*> pip_to_net; - std::vector<NetInfo*> switches_locked; + std::vector<CellInfo *> bel_to_cell; + std::vector<NetInfo *> wire_to_net; + std::vector<NetInfo *> pip_to_net; + std::vector<NetInfo *> switches_locked; ArchArgs args; Arch(ArchArgs args); @@ -411,6 +411,7 @@ struct Arch : BaseCtx std::string getChipName() const; IdString archId() const { return id("ice40"); } + ArchArgs archArgs() const { return args; } IdString archArgsToId(ArchArgs args) const; // ------------------------------------------------- @@ -782,16 +783,15 @@ struct Arch : BaseCtx // Get the delay through a cell from one port to another, returning false // if no path exists bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; - // Get the associated clock to a port, or empty if the port is combinational - IdString getPortClock(const CellInfo *cell, IdString port) const; - // Return true if a port is a clock - bool isClockPort(const CellInfo *cell, IdString port) const; + // Get the port class, also setting clockDomain if applicable + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockDomain) const; // Return true if a port is a net bool isGlobalNet(const NetInfo *net) const; // ------------------------------------------------- - // Perform placement validity checks, returning false on failure (all implemented in arch_place.cc) + // Perform placement validity checks, returning false on failure (all + // implemented in arch_place.cc) // Whether or not a given cell can be placed at a given Bel // This is not intended for Bel type checks, but finer-grained constraints @@ -805,7 +805,8 @@ struct Arch : BaseCtx bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const; // ------------------------------------------------- - // Assign architecure-specific arguments to nets and cells, which must be called between packing or further + // Assign architecure-specific arguments to nets and cells, which must be + // called between packing or further // netlist modifications, and validity checks void assignArchInfo(); void assignCellInfo(CellInfo *cell); |