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-rw-r--r--fpga_interchange/examples/chipdb.cmake112
-rw-r--r--fpga_interchange/examples/create_bba/Makefile93
-rw-r--r--fpga_interchange/examples/create_bba/README.md40
-rw-r--r--fpga_interchange/examples/devices/CMakeLists.txt1
-rw-r--r--fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt2
-rw-r--r--fpga_interchange/family.cmake7
6 files changed, 122 insertions, 133 deletions
diff --git a/fpga_interchange/examples/chipdb.cmake b/fpga_interchange/examples/chipdb.cmake
new file mode 100644
index 00000000..5f1e4a67
--- /dev/null
+++ b/fpga_interchange/examples/chipdb.cmake
@@ -0,0 +1,112 @@
+function(create_rapidwright_device_db)
+ set(options)
+ set(oneValueArgs part)
+ set(multiValueArgs)
+
+ cmake_parse_arguments(
+ create_rapidwright_device_db
+ "${options}"
+ "${oneValueArgs}"
+ "${multiValueArgs}"
+ ${ARGN}
+ )
+
+ set(part ${create_rapidwright_device_db_part})
+ set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
+ add_custom_command(
+ OUTPUT ${rapidwright_device_db}
+ COMMAND
+ RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
+ ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
+ com.xilinx.rapidwright.interchange.DeviceResourcesExample
+ ${part}
+ DEPENDS
+ ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh
+ )
+
+ add_custom_target(rapidwright-${part}-device DEPENDS ${rapidwright_device_db})
+ set_property(TARGET rapidwright-${part}-device PROPERTY LOCATION ${rapidwright_device_db})
+endfunction()
+
+function(generate_chipdb)
+ set(options)
+ set(oneValueArgs part)
+ set(multiValueArgs)
+
+ cmake_parse_arguments(
+ generate_chipdb
+ "${options}"
+ "${oneValueArgs}"
+ "${multiValueArgs}"
+ ${ARGN}
+ )
+
+ set(part ${generate_chipdb_part})
+
+ create_rapidwright_device_db(part ${part})
+
+ set(rapidwright_device_target rapidwright-${part}-device)
+ get_property(rapidwright_device_loc TARGET ${rapidwright_device_target} PROPERTY LOCATION)
+
+ set(constraints_device ${CMAKE_CURRENT_BINARY_DIR}/${part}_constraints.device)
+ add_custom_command(
+ OUTPUT ${constraints_device}
+ COMMAND
+ python3 -mfpga_interchange.patch
+ --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+ --schema device
+ --patch_path constraints
+ --patch_format yaml
+ ${rapidwright_device_loc}
+ ${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
+ ${constraints_device}
+ DEPENDS
+ ${rapidwright_device_target}
+ )
+
+ add_custom_target(constraints-${part}-device DEPENDS ${constraints_device})
+
+ set(constraints_luts_device ${CMAKE_CURRENT_BINARY_DIR}/${part}_constraints_luts.device)
+ add_custom_command(
+ OUTPUT ${constraints_luts_device}
+ COMMAND
+ python3 -mfpga_interchange.patch
+ --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+ --schema device
+ --patch_path lutDefinitions
+ --patch_format yaml
+ ${constraints_device}
+ ${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
+ ${constraints_luts_device}
+ DEPENDS
+ ${constraints_device}
+ )
+
+ add_custom_target(constraints-luts-${part}-device DEPENDS ${constraints_luts_device})
+ set_property(TARGET constraints-luts-${part}-device PROPERTY LOCATION ${constraints_luts_device})
+
+ set(chipdb_bba ${chipdb_dir}/chipdb-${part}.bba)
+ add_custom_command(
+ OUTPUT ${chipdb_bba}
+ COMMAND
+ python3 -mfpga_interchange.nextpnr_emit
+ --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+ --output_dir ${chipdb_dir}
+ --bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
+ --device ${constraints_luts_device}
+ COMMAND
+ mv ${chipdb_dir}/chipdb.bba ${chipdb_bba}
+ DEPENDS
+ ${constraints_luts_device}
+ )
+
+ add_custom_target(chipdb-${part}-bba DEPENDS ${chipdb_bba})
+ add_dependencies(chipdb-${family}-bbas chipdb-${part}-bba)
+endfunction()
+
+set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
+file(MAKE_DIRECTORY ${chipdb_dir})
+
+add_custom_target(chipdb-${family}-bbas)
+
+add_subdirectory(${family}/examples/devices)
diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile
deleted file mode 100644
index c29bfa82..00000000
--- a/fpga_interchange/examples/create_bba/Makefile
+++ /dev/null
@@ -1,93 +0,0 @@
-#
-# nextpnr -- Next Generation Place and Route
-#
-# Copyright (C) 2021 Symbiflow Authors
-#
-#
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
-#
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-
-
-# This Makefile provides a streamlined way to create an example
-# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts.
-#
-# FPGA interchange device database is generated via RapidWright.
-#
-# Currently FPGA interchange physical netlist (e.g. place and route route) to
-# FASM support is not done, so bitstream generation relies on RapidWright to
-# convert FPGA interchange logical and physical netlist into a Vivado DCP.
-
-include ../common.mk
-
-.DELETE_ON_ERROR:
-
-.PHONY: all chipdb test debug_test
-
-all: chipdb
-
-build:
- mkdir build
-
-build/RapidWright: | build
- cd build && git clone https://github.com/Xilinx/RapidWright.git
-
-build/env: | build
- python3 -mvenv build/env
-
-build/python-fpga-interchange: | build
- cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git
-
-build/fpga-interchange-schema: | build
- cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git
-
-build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright
- source build/env/bin/activate && \
- cd build/python-fpga-interchange/ && \
- pip install -r requirements.txt
- touch build/.setup
-
-$(NEXTPNR_PATH)/build:
- mkdir $(NEXTPNR_PATH)/build
-
-$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
- cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
- make -j -C $(NEXTPNR_PATH)/build
-
-build/nextpnr/fpga_interchange/chipdb.bba: build/.setup
- mkdir -p build/nextpnr/fpga_interchange
- source build/env/bin/activate && \
- cd build/python-fpga-interchange/ && \
- make \
- -f Makefile.rapidwright \
- NEXTPNR_PATH=$(realpath .)/build/nextpnr \
- RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
- INTERCHANGE_PATH=$(INTERCHANGE_PATH)
-
-$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm build/nextpnr/fpga_interchange/chipdb.bba
- $(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
-
-chipdb: $(BBA_PATH)
-
-test: chipdb
- $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
- --chipdb $(BBA_PATH) \
- --package csg324 \
- --test
-
-debug_test: chipdb
- gdb --args $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
- --chipdb $(BBA_PATH) \
- --package csg324 \
- --test
-
-clean:
- rm -rf build
diff --git a/fpga_interchange/examples/create_bba/README.md b/fpga_interchange/examples/create_bba/README.md
deleted file mode 100644
index d2ca5188..00000000
--- a/fpga_interchange/examples/create_bba/README.md
+++ /dev/null
@@ -1,40 +0,0 @@
-## Makefile-driven BBA creation
-
-This Makefile will generate a Xilinx A35 chipdb if java, capnproto and
-capnproto-java are installed.
-
-### Installing dependencies
-
-Install java and javac if not already installed:
-```
-# Or equivalent for your local system.
-sudo apt-get install openjdk-10-jdk
-```
-
-Install capnproto if not already installed:
-```
-# Or equivalent for your local system.
-sudo apt-get install capnproto libcapnp-dev
-```
-
-Install capnproto-java if not already installed:
-```
-git clone https://github.com/capnproto/capnproto-java.git
-cd capnproto-java
-make
-sudo make install
-```
-
-### Instructions
-
-Once dependencies are installed, just run "make". This should download
-remaining dependencies and build the chipdb and build nextpnr if not built.
-
-#### Re-building the chipdb
-
-```
-# Remove the text BBA
-rm build/nextpnr/fpga_interchange/chipdb.bba
-# Build the BBA
-make
-```
diff --git a/fpga_interchange/examples/devices/CMakeLists.txt b/fpga_interchange/examples/devices/CMakeLists.txt
new file mode 100644
index 00000000..5b96ac80
--- /dev/null
+++ b/fpga_interchange/examples/devices/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(xc7a35t)
diff --git a/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
new file mode 100644
index 00000000..2b0dce53
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
@@ -0,0 +1,2 @@
+generate_chipdb(part xc7a35tcsg324-1)
+generate_chipdb(part xc7a35tcpg236-1)
diff --git a/fpga_interchange/family.cmake b/fpga_interchange/family.cmake
index e62ab458..112cb3dc 100644
--- a/fpga_interchange/family.cmake
+++ b/fpga_interchange/family.cmake
@@ -5,7 +5,14 @@ endif()
find_package(ZLIB REQUIRED)
+set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
+# FIXME: Make patch data available in the python package and remove this cached var
+set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
+set(INTERCHANGE_SCHEMA_PATH $ENV{HOME}/fpga_interchange_schema CACHE PATH "Path to the FPGA interchange schema dir")
+
add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
+include(${family}/examples/chipdb.cmake)
+include(${family}/examples/tests.cmake)
foreach (target ${family_targets})
target_include_directories(${target} PRIVATE ${TCL_INCLUDE_PATH})
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 21:04:55 +0000