3 files changed, 49 insertions, 11 deletions
diff --git a/fpga_interchange/examples/devices/CMakeLists.txt b/fpga_interchange/examples/devices/CMakeLists.txt
index 6a60d4f8..5b96ac80 100644
--- a/fpga_interchange/examples/devices/CMakeLists.txt
+++ b/fpga_interchange/examples/devices/CMakeLists.txt
@@ -1,11 +1 @@
-generate_xc7_device_db(
-    device xc7a35t
-    part xc7a35tcsg324-1
-)
-
-generate_chipdb(
-    device xc7a35t
-    part xc7a35tcsg324-1
-    device_target ${device_target}
-    bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
-)
+add_subdirectory(xc7a35t)
diff --git a/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt b/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
new file mode 100644
index 00000000..a7a49751
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
@@ -0,0 +1,12 @@
+generate_xc7_device_db(
+    device xc7a35t
+    part xc7a35tcsg324-1
+)
+
+generate_chipdb(
+    device xc7a35t
+    part xc7a35tcsg324-1
+    device_target ${device_target}
+    bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
+    package csg324
+)
diff --git a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
new file mode 100644
index 00000000..268d180a
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+      dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+        - INT_R_X3Y145/GND_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+        - INT_R_X3Y145/VCC_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+    - bel: SLICE_X15Y93.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X15Y93.SLICEL/D3
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+      pin: G
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+      pin: P
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE