4 files changed, 0 insertions, 39 deletions
diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile
deleted file mode 100644
index 49194f53..00000000
--- a/fpga_interchange/examples/const_wire/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-DESIGN := wire
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/wire.json: wire.v | build
-	yosys -c run.tcl
diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl
deleted file mode 100644
index 9127be20..00000000
--- a/fpga_interchange/examples/const_wire/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog wire.v
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json build/wire.json
diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v
deleted file mode 100644
index 5b1ab692..00000000
--- a/fpga_interchange/examples/const_wire/wire.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module top(output o, output o2, output o3, output o4);
-
-assign o = 1'b0;
-assign o2 = 1'b1;
-assign o3 = 1'b0;
-assign o4 = 1'b1;
-
-endmodule
diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc
deleted file mode 100644
index 0d96fc45..00000000
--- a/fpga_interchange/examples/const_wire/wire.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-set_property PACKAGE_PIN N15 [get_ports o]
-set_property PACKAGE_PIN N16 [get_ports o2]
-set_property PACKAGE_PIN P17 [get_ports o3]
-set_property PACKAGE_PIN R17 [get_ports o4]
-
-set_property IOSTANDARD LVCMOS33 [get_ports o]
-set_property IOSTANDARD LVCMOS33 [get_ports o2]
-set_property IOSTANDARD LVCMOS33 [get_ports o3]
-set_property IOSTANDARD LVCMOS33 [get_ports o4]