diff options
Diffstat (limited to 'fpga_interchange/chipdb.h')
| -rw-r--r-- | fpga_interchange/chipdb.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 155c2bb2..78d9c1c5 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -402,6 +402,27 @@ NPNR_PACKED_STRUCT(struct MacroExpansionPOD { RelSlice<MacroParamMapRulePOD> param_rules; }); +NPNR_PACKED_STRUCT(struct ClusterCellPortPOD { + uint32_t cell; + uint32_t port; +}); + +NPNR_PACKED_STRUCT(struct ChainablePortPOD { + uint32_t cell_source; + uint32_t cell_sink; + uint32_t bel_source; + uint32_t bel_sink; + int16_t avg_x_offset; + int16_t avg_y_offset; +}); + +NPNR_PACKED_STRUCT(struct ClusterPOD { + uint32_t name; + RelSlice<uint32_t> root_cell_types; + RelSlice<ChainablePortPOD> chainable_ports; + RelSlice<ClusterCellPortPOD> cluster_cells_map; +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<char> name; RelPtr<char> generator; @@ -421,6 +442,8 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelSlice<MacroPOD> macros; RelSlice<MacroExpansionPOD> macro_rules; + RelSlice<ClusterPOD> clusters; + // BEL bucket constids. RelSlice<int32_t> bel_buckets; @@ -460,6 +483,11 @@ inline const SiteInstInfoPOD &site_inst_info(const ChipInfoPOD *chip_info, int32 return chip_info->sites[chip_info->tiles[tile].sites[site]]; } +inline const ClusterPOD &cluster_info(const ChipInfoPOD *chip_info, int32_t cluster) +{ + return chip_info->clusters[cluster]; +} + enum SyntheticType { NOT_SYNTH = 0, |