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-rw-r--r--ecp5/arch.cc46
-rw-r--r--ecp5/arch.h3
-rw-r--r--ecp5/arch_place.cc7
-rw-r--r--ecp5/bitstream.cc43
-rw-r--r--ecp5/main.cc4
5 files changed, 60 insertions, 43 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 7d67dd0c..5507d1e3 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -192,17 +192,20 @@ BelId Arch::getBelByName(IdString name) const
return ret;
}
-BelRange Arch::getBelsAtSameTile(BelId bel) const
+BelRange Arch::getBelsByTile(int x, int y) const
{
BelRange br;
- NPNR_ASSERT(bel != BelId());
- br.b.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
- br.e.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
+
+ br.b.cursor_tile = y * chip_info->width + x;
+ br.e.cursor_tile = y * chip_info->width + x;
br.b.cursor_index = 0;
- br.e.cursor_index = locInfo(bel)->num_bels - 1;
+ br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].num_bels - 1;
br.b.chip = chip_info;
br.e.chip = chip_info;
- ++br.e;
+ if (br.e.cursor_index == -1)
+ ++br.e.cursor_index;
+ else
+ ++br.e;
return br;
}
@@ -278,6 +281,7 @@ PipId Arch::getPipByName(IdString name) const
Location loc;
std::string basename;
std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
+ ret.location = loc;
const LocationTypePOD *loci = locInfo(ret);
for (int i = 0; i < loci->num_pips; i++) {
PipId curr;
@@ -285,6 +289,8 @@ PipId Arch::getPipByName(IdString name) const
curr.index = i;
pip_by_name[getPipName(curr)] = curr;
}
+ if (pip_by_name.find(name) == pip_by_name.end())
+ NPNR_ASSERT_FALSE_STR("no pip named " + name.str(this));
return pip_by_name[name];
}
@@ -399,36 +405,8 @@ BelId Arch::getBelByLocation(Loc loc) const
return BelId();
}
-BelRange Arch::getBelsByTile(int x, int y) const
-{
- BelRange br;
-
- int num_bels = 0;
-
- if (x < chip_info->width && y < chip_info->height) {
- const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[y * chip_info->width + x]];
- num_bels = locI.num_bels;
- }
-
- br.b.cursor_tile = y * chip_info->width + x;
- br.e.cursor_tile = y * chip_info->width + x;
- br.b.cursor_index = 0;
- br.e.cursor_index = num_bels - 1;
- br.b.chip = chip_info;
- br.e.chip = chip_info;
- ++br.e;
- return br;
-}
-
// -----------------------------------------------------------------------
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
- x = bel.location.x;
- y = bel.location.y;
- gb = false;
-}
-
delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
diff --git a/ecp5/arch.h b/ecp5/arch.h
index ce2b90c3..4400db5e 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -482,8 +482,6 @@ struct Arch : BaseCtx
return range;
}
- BelRange getBelsAtSameTile(BelId bel) const;
-
BelType getBelType(BelId bel) const
{
NPNR_ASSERT(bel != BelId());
@@ -752,7 +750,6 @@ struct Arch : BaseCtx
// -------------------------------------------------
- void estimatePosition(BelId bel, int &x, int &y, bool &gb) const;
delay_t estimateDelay(WireId src, WireId dst) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 22ebab67..84432043 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -66,7 +66,8 @@ bool Arch::isBelLocationValid(BelId bel) const
{
if (getBelType(bel) == TYPE_TRELLIS_SLICE) {
std::vector<const CellInfo *> bel_cells;
- for (auto bel_other : getBelsAtSameTile(bel)) {
+ Loc bel_loc = getBelLocation(bel);
+ for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
IdString cell_other = getBoundBelCell(bel_other);
if (cell_other != IdString()) {
const CellInfo *ci_other = cells.at(cell_other).get();
@@ -89,8 +90,8 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
NPNR_ASSERT(getBelType(bel) == TYPE_TRELLIS_SLICE);
std::vector<const CellInfo *> bel_cells;
-
- for (auto bel_other : getBelsAtSameTile(bel)) {
+ Loc bel_loc = getBelLocation(bel);
+ for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
IdString cell_other = getBoundBelCell(bel_other);
if (cell_other != IdString() && bel_other != bel) {
const CellInfo *ci_other = cells.at(cell_other).get();
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 19ddb9f9..c2218762 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -30,6 +30,7 @@
#include <fstream>
#include <streambuf>
+#include "io.h"
#include "log.h"
#include "util.h"
@@ -182,12 +183,34 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
}
}
+ // Find bank voltages
+ std::unordered_map<int, IOVoltage> bankVcc;
+ for (auto &cell : ctx->cells) {
+ CellInfo *ci = cell.second.get();
+ if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
+ int bank = ctx->getPioBelBank(ci->bel);
+ std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
+ IOVoltage vcc = get_vccio(ioType_from_str(iotype));
+ if (bankVcc.find(bank) != bankVcc.end()) {
+ // TODO: strong and weak constraints
+ if (bankVcc[bank] != vcc) {
+ log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
+ cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
+ iovoltage_to_str(vcc).c_str(), bank);
+ }
+ } else {
+ bankVcc[bank] = vcc;
+ }
+ }
+ }
- // Set all bankref tiles to 3.3V (TODO)
+ // Set all bankref tiles to appropriate VccIO
for (const auto &tile : empty_chip.tiles) {
std::string type = tile.second->info.type;
if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
- cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3");
+ int bank = std::stoi(type.substr(7));
+ if (bankVcc.find(bank) != bankVcc.end())
+ cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
}
}
@@ -235,6 +258,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string pic_tile = get_pic_tile(ctx, empty_chip, bel);
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+ if (is_differential(ioType_from_str(iotype))) {
+ // Explicitly disable other pair
+ std::string other;
+ if (pio == "PIOA")
+ other = "PIOB";
+ else if (pio == "PIOC")
+ other = "PIOD";
+ else
+ log_error("cannot place differential IO at location %s\n", pio.c_str());
+ cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+ cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+ cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
+ cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+ }
if (dir != "INPUT" &&
(ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
// Tie tristate low if unconnected for outputs or bidir
@@ -247,7 +284,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
}
- if (dir == "INPUT") {
+ if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
} else {
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 5a4a900a..90096855 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -63,6 +63,7 @@ int main(int argc, char *argv[])
#ifndef NO_GUI
options.add_options()("gui", "start gui");
#endif
+ options.add_options()("test", "check architecture database integrity");
options.add_options()("25k", "set device type to LFE5U-25F");
options.add_options()("45k", "set device type to LFE5U-45F");
@@ -148,6 +149,9 @@ int main(int argc, char *argv[])
if (vm.count("no-tmdriv"))
ctx->timing_driven = false;
+ if (vm.count("test"))
+ ctx->archcheck();
+
#ifndef NO_GUI
if (vm.count("gui")) {
Application a(argc, argv);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 10:13:40 +0000