diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 8 | ||||
| -rw-r--r-- | ecp5/synth/wire.v | 11 | ||||
| -rw-r--r-- | ecp5/synth/wire.ys | 9 |
3 files changed, 27 insertions, 1 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index e80ad829..d0dc63f0 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -218,11 +218,14 @@ WireId Arch::getWireByName(IdString name) const for (int i = 0; i < loci->num_wires; i++) { if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) { ret.index = i; + ret.location = loc; break; } } if (ret.index >= 0) wire_by_name[name] = ret; + else + ret.location = Location(); return ret; } @@ -278,7 +281,10 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const gb = false; } -delay_t Arch::estimateDelay(WireId src, WireId dst) const { return 1; } +delay_t Arch::estimateDelay(WireId src, WireId dst) const +{ + return abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y); +} // ----------------------------------------------------------------------- diff --git a/ecp5/synth/wire.v b/ecp5/synth/wire.v new file mode 100644 index 00000000..2af68ed2 --- /dev/null +++ b/ecp5/synth/wire.v @@ -0,0 +1,11 @@ +module top(input a_pin, output [3:0] led_pin); + + wire a; + wire [3:0] led; + + TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a)); + TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led)); + + //assign led[0] = !a; + always @(posedge a) led[0] <= !led[0]; +endmodule diff --git a/ecp5/synth/wire.ys b/ecp5/synth/wire.ys new file mode 100644 index 00000000..f916588b --- /dev/null +++ b/ecp5/synth/wire.ys @@ -0,0 +1,9 @@ +read_verilog wire.v +read_verilog -lib cells.v +synth -top top +abc -lut 4 +techmap -map simple_map.v +splitnets +opt_clean +stat +write_json wire.json |