diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 92 | ||||
| -rw-r--r-- | ecp5/arch.h | 40 | ||||
| -rw-r--r-- | ecp5/arch_place.cc | 7 | ||||
| -rw-r--r-- | ecp5/arch_pybindings.cc | 125 | ||||
| -rw-r--r-- | ecp5/bitstream.cc | 58 | ||||
| -rw-r--r-- | ecp5/family.cmake | 20 | ||||
| -rw-r--r-- | ecp5/io.cc | 217 | ||||
| -rw-r--r-- | ecp5/io.h | 70 | ||||
| -rw-r--r-- | ecp5/iotypes.inc | 37 | ||||
| -rw-r--r-- | ecp5/main.cc | 20 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 349 |
11 files changed, 679 insertions, 356 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index d887aa69..b070014e 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -192,17 +192,20 @@ BelId Arch::getBelByName(IdString name) const return ret; } -BelRange Arch::getBelsAtSameTile(BelId bel) const +BelRange Arch::getBelsByTile(int x, int y) const { BelRange br; - NPNR_ASSERT(bel != BelId()); - br.b.cursor_tile = bel.location.y * chip_info->width + bel.location.x; - br.e.cursor_tile = bel.location.y * chip_info->width + bel.location.x; + + br.b.cursor_tile = y * chip_info->width + x; + br.e.cursor_tile = y * chip_info->width + x; br.b.cursor_index = 0; - br.e.cursor_index = locInfo(bel)->num_bels - 1; + br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].num_bels - 1; br.b.chip = chip_info; br.e.chip = chip_info; - ++br.e; + if (br.e.cursor_index == -1) + ++br.e.cursor_index; + else + ++br.e; return br; } @@ -278,6 +281,7 @@ PipId Arch::getPipByName(IdString name) const Location loc; std::string basename; std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this)); + ret.location = loc; const LocationTypePOD *loci = locInfo(ret); for (int i = 0; i < loci->num_pips; i++) { PipId curr; @@ -285,6 +289,8 @@ PipId Arch::getPipByName(IdString name) const curr.index = i; pip_by_name[getPipName(curr)] = curr; } + if (pip_by_name.find(name) == pip_by_name.end()) + NPNR_ASSERT_FALSE_STR("no pip named " + name.str(this)); return pip_by_name[name]; } @@ -322,13 +328,52 @@ BelId Arch::getPackagePinBel(const std::string &pin) const std::string Arch::getBelPackagePin(BelId bel) const { for (int i = 0; i < package_info->num_pins; i++) { - if (package_info->pin_data[i].abs_loc == bel.location && package_info->pin_data[i].bel_index == bel.index) { + if (Location(package_info->pin_data[i].abs_loc) == bel.location && + package_info->pin_data[i].bel_index == bel.index) { return package_info->pin_data[i].name.get(); } } return ""; } +int Arch::getPioBelBank(BelId bel) const +{ + for (int i = 0; i < chip_info->num_pios; i++) { + if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) { + return chip_info->pio_info[i].bank; + } + } + NPNR_ASSERT_FALSE("failed to find PIO"); +} + +std::string Arch::getPioFunctionName(BelId bel) const +{ + for (int i = 0; i < chip_info->num_pios; i++) { + if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) { + const char *func = chip_info->pio_info[i].function_name.get(); + if (func == nullptr) + return ""; + else + return func; + } + } + NPNR_ASSERT_FALSE("failed to find PIO"); +} + +BelId Arch::getPioByFunctionName(const std::string &name) const +{ + for (int i = 0; i < chip_info->num_pios; i++) { + const char *func = chip_info->pio_info[i].function_name.get(); + if (func != nullptr && func == name) { + BelId bel; + bel.location = chip_info->pio_info[i].abs_loc; + bel.index = chip_info->pio_info[i].bel_index; + return bel; + } + } + return BelId(); +} + std::vector<PortPin> Arch::getBelPins(BelId bel) const { @@ -361,45 +406,14 @@ BelId Arch::getBelByLocation(Loc loc) const return BelId(); } -BelRange Arch::getBelsByTile(int x, int y) const -{ - BelRange br; - - int num_bels = 0; - - if (x < chip_info->width && y < chip_info->height) { - const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[y * chip_info->width + x]]; - num_bels = locI.num_bels; - } - - br.b.cursor_tile = y * chip_info->width + x; - br.e.cursor_tile = y * chip_info->width + x; - br.b.cursor_index = 0; - br.e.cursor_index = num_bels - 1; - br.b.chip = chip_info; - br.e.chip = chip_info; - ++br.e; - return br; -} - // ----------------------------------------------------------------------- -void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const -{ - x = bel.location.x; - y = bel.location.y; - gb = false; -} - delay_t Arch::estimateDelay(WireId src, WireId dst) const { return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y)); } -delay_t Arch::getBudgetOverride(const PortRef& pr, delay_t v) const -{ - return v; -} +delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; } // ----------------------------------------------------------------------- diff --git a/ecp5/arch.h b/ecp5/arch.h index 38362d6b..445f0dbf 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -98,7 +98,7 @@ NPNR_PACKED_STRUCT(struct LocationTypePOD { }); NPNR_PACKED_STRUCT(struct PIOInfoPOD { - Location abs_loc; + LocationPOD abs_loc; int32_t bel_index; RelPtr<char> function_name; int16_t bank; @@ -107,7 +107,7 @@ NPNR_PACKED_STRUCT(struct PIOInfoPOD { NPNR_PACKED_STRUCT(struct PackagePinPOD { RelPtr<char> name; - Location abs_loc; + LocationPOD abs_loc; int32_t bel_index; }); @@ -117,6 +117,26 @@ NPNR_PACKED_STRUCT(struct PackageInfoPOD { RelPtr<PackagePinPOD> pin_data; }); +enum TapDirection : int8_t +{ + TAP_DIR_LEFT = 0, + TAP_DIR_RIGHT = 1 +}; + +enum GlobalQuadrant : int8_t +{ + QUAD_UL = 0, + QUAD_UR = 1, + QUAD_LL = 2, + QUAD_LR = 3, +}; + +NPNR_PACKED_STRUCT(struct GlobalInfoPOD { + int16_t tap_col; + TapDirection tap_dir; + GlobalQuadrant quad; +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t width, height; int32_t num_tiles; @@ -124,6 +144,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t num_packages, num_pios; RelPtr<LocationTypePOD> locations; RelPtr<int32_t> location_type; + RelPtr<GlobalInfoPOD> location_glbinfo; RelPtr<RelPtr<char>> tiletype_names; RelPtr<PackageInfoPOD> package_info; RelPtr<PIOInfoPOD> pio_info; @@ -482,8 +503,6 @@ struct Arch : BaseCtx return range; } - BelRange getBelsAtSameTile(BelId bel) const; - BelType getBelType(BelId bel) const { NPNR_ASSERT(bel != BelId()); @@ -519,6 +538,8 @@ struct Arch : BaseCtx return id(name.str()); } + IdString getWireType(WireId wire) const { return IdString(); } + uint32_t getWireChecksum(WireId wire) const { return wire.index; } void bindWire(WireId wire, IdString net, PlaceStrength strength) @@ -597,6 +618,8 @@ struct Arch : BaseCtx PipId getPipByName(IdString name) const; IdString getPipName(PipId pip) const; + IdString getPipType(PipId pip) const { return IdString(); } + uint32_t getPipChecksum(PipId pip) const { return pip.index; } void bindPip(PipId pip, IdString net, PlaceStrength strength) @@ -729,10 +752,14 @@ struct Arch : BaseCtx return chip_info->tiletype_names[locInfo(pip)->pip_data[pip.index].tile_type].get(); } - int8_t getPipType(PipId pip) const { return locInfo(pip)->pip_data[pip.index].pip_type; } + int8_t getPipClass(PipId pip) const { return locInfo(pip)->pip_data[pip.index].pip_type; } BelId getPackagePinBel(const std::string &pin) const; std::string getBelPackagePin(BelId bel) const; + int getPioBelBank(BelId bel) const; + // For getting GCLK, PLL, Vref, etc, pins + std::string getPioFunctionName(BelId bel) const; + BelId getPioByFunctionName(const std::string &name) const; PortType getBelPinType(BelId bel, PortPin pin) const; @@ -748,13 +775,12 @@ struct Arch : BaseCtx // ------------------------------------------------- - void estimatePosition(BelId bel, int &x, int &y, bool &gb) const; delay_t estimateDelay(WireId src, WireId dst) const; delay_t getDelayEpsilon() const { return 20; } delay_t getRipupDelayPenalty() const { return 200; } float getDelayNS(delay_t v) const { return v * 0.001; } uint32_t getDelayChecksum(delay_t v) const { return v; } - delay_t getBudgetOverride(const PortRef& pr, delay_t v) const; + delay_t getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const; // ------------------------------------------------- diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc index 22ebab67..84432043 100644 --- a/ecp5/arch_place.cc +++ b/ecp5/arch_place.cc @@ -66,7 +66,8 @@ bool Arch::isBelLocationValid(BelId bel) const { if (getBelType(bel) == TYPE_TRELLIS_SLICE) { std::vector<const CellInfo *> bel_cells; - for (auto bel_other : getBelsAtSameTile(bel)) { + Loc bel_loc = getBelLocation(bel); + for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) { IdString cell_other = getBoundBelCell(bel_other); if (cell_other != IdString()) { const CellInfo *ci_other = cells.at(cell_other).get(); @@ -89,8 +90,8 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const NPNR_ASSERT(getBelType(bel) == TYPE_TRELLIS_SLICE); std::vector<const CellInfo *> bel_cells; - - for (auto bel_other : getBelsAtSameTile(bel)) { + Loc bel_loc = getBelLocation(bel); + for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) { IdString cell_other = getBoundBelCell(bel_other); if (cell_other != IdString() && bel_other != bel) { const CellInfo *ci_other = cells.at(cell_other).get(); diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc index 8310c3a1..c261c3ec 100644 --- a/ecp5/arch_pybindings.cc +++ b/ecp5/arch_pybindings.cc @@ -2,7 +2,7 @@ * nextpnr -- Next Generation Place and Route * * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 David Shah <dave@ds0.me> + * Copyright (C) 2018 David Shah <david@symbioticeda.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -20,13 +20,132 @@ #ifndef NO_PYTHON +#include "arch_pybindings.h" #include "nextpnr.h" #include "pybindings.h" NEXTPNR_NAMESPACE_BEGIN -void arch_wrap_python() {} +void arch_wrap_python() +{ + using namespace PythonConversion; + class_<ArchArgs>("ArchArgs").def_readwrite("type", &ArchArgs::type); + + class_<BelId>("BelId").def_readwrite("index", &BelId::index); + + class_<WireId>("WireId").def_readwrite("index", &WireId::index); + + class_<PipId>("PipId").def_readwrite("index", &PipId::index); + + class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin); + + enum_<PortPin>("PortPin") +#define X(t) .value("PIN_" #t, PIN_##t) + +#include "portpins.inc" + ; +#undef X + + auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>()); + auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init) + .def("checksum", &Context::checksum) + .def("pack", &Context::pack) + .def("place", &Context::place) + .def("route", &Context::route); + + fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<BelType>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType"); + fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap( + ctx_cls, "unbindBel"); + fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, conv_to_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell, + conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell"); + fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls, + "getBels"); + + fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>, + conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire"); + fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins"); + + fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap( + ctx_cls, "unbindWire"); + fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, conv_to_str<IdString>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet, + conv_to_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet"); + + fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap( + ctx_cls, "getWires"); + + fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap( + ctx_cls, "getPips"); + fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap( + ctx_cls, "unbindPip"); + fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, conv_to_str<IdString>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet, + conv_to_str<IdString>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet"); + + fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsDownhill"); + fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill"); + fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases"); + + fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay"); + + fn_wrapper_1a<Context, decltype(&Context::getPackagePinBel), &Context::getPackagePinBel, conv_to_str<BelId>, + pass_through<std::string>>::def_wrap(ctx_cls, "getPackagePinBel"); + fn_wrapper_1a<Context, decltype(&Context::getBelPackagePin), &Context::getBelPackagePin, pass_through<std::string>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelPackagePin"); + + fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap( + ctx_cls, "getChipName"); + fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls, + "archId"); + + typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; + typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; + + readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls, + "cells"); + readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls, + "nets"); + WRAP_RANGE(Bel, conv_to_str<BelId>); + WRAP_RANGE(Wire, conv_to_str<WireId>); + WRAP_RANGE(AllPip, conv_to_str<PipId>); + WRAP_RANGE(Pip, conv_to_str<PipId>); + + WRAP_MAP_UPTR(CellMap, "IdCellMap"); + WRAP_MAP_UPTR(NetMap, "IdNetMap"); +} NEXTPNR_NAMESPACE_END -#endif +#endif // NO_PYTHON diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 19ddb9f9..df9b12d5 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -30,6 +30,7 @@ #include <fstream> #include <streambuf> +#include "io.h" #include "log.h" #include "util.h" @@ -173,7 +174,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { if (ctx->getBoundPipNet(pip) != IdString()) { - if (ctx->getPipType(pip) == 0) { // ignore fixed pips + if (ctx->getPipClass(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); @@ -182,12 +183,47 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } } } + // Find bank voltages + std::unordered_map<int, IOVoltage> bankVcc; + std::unordered_map<int, bool> bankLvds; - // Set all bankref tiles to 3.3V (TODO) + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) { + int bank = ctx->getPioBelBank(ci->bel); + std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); + std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); + + if (dir != "INPUT") { + IOVoltage vcc = get_vccio(ioType_from_str(iotype)); + if (bankVcc.find(bank) != bankVcc.end()) { + // TODO: strong and weak constraints + if (bankVcc[bank] != vcc) { + log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", + cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), + iovoltage_to_str(vcc).c_str(), bank); + } + } else { + bankVcc[bank] = vcc; + } + } + + if (iotype == "LVDS") + bankLvds[bank] = true; + } + } + + // Set all bankref tiles to appropriate VccIO for (const auto &tile : empty_chip.tiles) { std::string type = tile.second->info.type; if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { - cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3"); + int bank = std::stoi(type.substr(7)); + if (bankVcc.find(bank) != bankVcc.end()) + cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); + if (bankLvds[bank]) { + cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON"); + cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON"); + } } } @@ -235,6 +271,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string pic_tile = get_pic_tile(ctx, empty_chip, bel); cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); + if (is_differential(ioType_from_str(iotype))) { + // Explicitly disable other pair + std::string other; + if (pio == "PIOA") + other = "PIOB"; + else if (pio == "PIOC") + other = "PIOD"; + else + log_error("cannot place differential IO at location %s\n", pio.c_str()); + // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); + cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); + } if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir @@ -247,7 +297,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get(); cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0"); } - if (dir == "INPUT") { + if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) { cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON"); } } else { diff --git a/ecp5/family.cmake b/ecp5/family.cmake index 97e5d66b..1c388e99 100644 --- a/ecp5/family.cmake +++ b/ecp5/family.cmake @@ -24,11 +24,16 @@ if (MSVC) set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resources/chipdb.rc PROPERTIES LANGUAGE RC) foreach (dev ${devices}) set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bin) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/portpins.inc) - add_custom_command(OUTPUT ${DEV_CC_DB} - COMMAND ${ENV_CMD} python3 ${DB_PY} -b -p ${DEV_PORTS_INC} ${dev} ${DEV_CC_DB} + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_PORTS_INC} ${dev} > ${DEV_CC_BBA_DB} DEPENDS ${DB_PY} ) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB} + DEPENDS bbasm ${DEV_CC_BBA_DB} + ) target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) foreach (target ${family_targets}) @@ -39,11 +44,18 @@ else() target_compile_options(ecp5_chipdb PRIVATE -g0 -O0 -w) foreach (dev ${devices}) set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.cc) + set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba) set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/portpins.inc) - add_custom_command(OUTPUT ${DEV_CC_DB} - COMMAND ${ENV_CMD} python3 ${DB_PY} -c -p ${DEV_PORTS_INC} ${dev} ${DEV_CC_DB} + add_custom_command(OUTPUT ${DEV_CC_BBA_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -p ${DEV_PORTS_INC} ${dev} > ${DEV_CC_BBA_DB}.new + COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB} DEPENDS ${DB_PY} ) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new + COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB} + DEPENDS bbasm ${DEV_CC_BBA_DB} + ) target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) foreach (target ${family_targets}) target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb>) diff --git a/ecp5/io.cc b/ecp5/io.cc new file mode 100644 index 00000000..e86c84f6 --- /dev/null +++ b/ecp5/io.cc @@ -0,0 +1,217 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "io.h" + +NEXTPNR_NAMESPACE_BEGIN + +std::string iovoltage_to_str(IOVoltage v) +{ + switch (v) { + case IOVoltage::VCC_3V3: + return "3V3"; + case IOVoltage::VCC_2V5: + return "2V5"; + case IOVoltage::VCC_1V8: + return "1V8"; + case IOVoltage::VCC_1V5: + return "1V5"; + case IOVoltage::VCC_1V35: + return "1V35"; + case IOVoltage::VCC_1V2: + return "1V2"; + } + NPNR_ASSERT_FALSE("unknown IO voltage"); +} + +IOVoltage iovoltage_from_str(const std::string &name) +{ + if (name == "3V3") + return IOVoltage::VCC_3V3; + if (name == "2V5") + return IOVoltage::VCC_2V5; + if (name == "1V8") + return IOVoltage::VCC_1V8; + if (name == "1V5") + return IOVoltage::VCC_1V5; + if (name == "1V35") + return IOVoltage::VCC_1V35; + if (name == "1V2") + return IOVoltage::VCC_1V2; + NPNR_ASSERT_FALSE("unknown IO voltage"); +} + +std::string iotype_to_str(IOType type) +{ + if (type == IOType::TYPE_NONE) + return "NONE"; +#define X(t) \ + if (type == IOType::t) \ + return #t; +#include "iotypes.inc" +#undef X + if (type == IOType::TYPE_UNKNOWN) + return "<unknown>"; + NPNR_ASSERT_FALSE("unknown IO type"); +} + +IOType ioType_from_str(const std::string &name) +{ + if (name == "NONE") + return IOType::TYPE_NONE; +#define X(t) \ + if (name == #t) \ + return IOType::t; +#include "iotypes.inc" + return IOType::TYPE_UNKNOWN; +} + +IOVoltage get_vccio(IOType type) +{ + switch (type) { + case IOType::LVTTL33: + case IOType::LVCMOS33: + case IOType::LVCMOS33D: + case IOType::LVPECL33: + case IOType::LVPECL33E: + return IOVoltage::VCC_3V3; + case IOType::LVCMOS25: + case IOType::LVCMOS25D: + case IOType::LVDS: + case IOType::SLVS: + case IOType::SUBLVDS: + case IOType::LVDS25E: + case IOType::MLVDS25: + case IOType::MLVDS25E: + case IOType::BLVDS25: + return IOVoltage::VCC_2V5; + case IOType::LVCMOS18: + case IOType::LVCMOS18D: + case IOType::SSTL18_I: + case IOType::SSTL18_II: + case IOType::SSTL18D_I: + case IOType::SSTL18D_II: + return IOVoltage::VCC_1V8; + case IOType::LVCMOS15: + case IOType::SSTL15_I: + case IOType::SSTL15_II: + case IOType::SSTL15D_I: + case IOType::SSTL15D_II: + return IOVoltage::VCC_1V5; + case IOType::SSTL135_I: + case IOType::SSTL135_II: + case IOType::SSTL135D_I: + case IOType::SSTL135D_II: + return IOVoltage::VCC_1V35; + case IOType::LVCMOS12: + case IOType::HSUL12: + case IOType::HSUL12D: + return IOVoltage::VCC_1V2; + default: + NPNR_ASSERT_FALSE("unknown IO type, unable to determine VccIO"); + } +} + +bool is_strong_vccio_constraint(IOType type, PortType dir, IOSide side) +{ + if (dir == PORT_OUT || dir == PORT_INOUT) + return true; + switch (type) { + case IOType::TYPE_NONE: + case IOType::LVCMOS33D: + case IOType::LVPECL33: + case IOType::LVDS: + case IOType::MLVDS25: + case IOType::BLVDS25: + case IOType::SLVS: + case IOType::SUBLVDS: + case IOType::LVCMOS12: + case IOType::HSUL12: + case IOType::HSUL12D: + return false; + case IOType::LVCMOS33: + case IOType::LVTTL33: + case IOType::LVCMOS25: + return (side == IOSide::LEFT || side == IOSide::RIGHT); + default: + return true; + } +} + +bool is_differential(IOType type) +{ + switch (type) { + case IOType::LVCMOS33D: + case IOType::LVCMOS25D: + case IOType::LVPECL33: + case IOType::LVDS: + case IOType::MLVDS25: + case IOType::BLVDS25: + case IOType::SLVS: + case IOType::SUBLVDS: + case IOType::LVCMOS18D: + case IOType::SSTL18D_I: + case IOType::SSTL18D_II: + case IOType::SSTL15D_I: + case IOType::SSTL15D_II: + case IOType::SSTL135D_I: + case IOType::SSTL135D_II: + case IOType::HSUL12D: + return true; + default: + return false; + } +} + +bool is_referenced(IOType type) +{ + switch (type) { + case IOType::SSTL18_I: + case IOType::SSTL18_II: + case IOType::SSTL18D_I: + case IOType::SSTL18D_II: + case IOType::SSTL15_I: + case IOType::SSTL15_II: + case IOType::SSTL15D_I: + case IOType::SSTL15D_II: + case IOType::SSTL135_I: + case IOType::SSTL135_II: + case IOType::SSTL135D_I: + case IOType::SSTL135D_II: + case IOType::HSUL12: + case IOType::HSUL12D: + return true; + default: + return false; + } +} + +bool valid_loc_for_io(IOType type, PortType dir, IOSide side, int z) +{ + bool is_lr = side == IOSide::LEFT || side == IOSide::RIGHT; + if (is_referenced(type) && !is_lr) + return false; + if (is_differential(type) && (!is_lr || ((z % 2) == 1))) + return false; + if ((type == IOType::LVCMOS18D || type == IOType::LVDS) && (dir == PORT_OUT || PORT_INOUT) && z != 0) + return false; + return true; +} + +NEXTPNR_NAMESPACE_END diff --git a/ecp5/io.h b/ecp5/io.h new file mode 100644 index 00000000..f0d941d9 --- /dev/null +++ b/ecp5/io.h @@ -0,0 +1,70 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah <david@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef IO_H +#define IO_H + +#include "nextpnr.h" + +NEXTPNR_NAMESPACE_BEGIN + +enum class IOVoltage +{ + VCC_3V3, + VCC_2V5, + VCC_1V8, + VCC_1V5, + VCC_1V35, + VCC_1V2 +}; + +std::string iovoltage_to_str(IOVoltage v); +IOVoltage iovoltage_from_str(const std::string &name); + +enum class IOType +{ + TYPE_NONE, +#define X(t) t, +#include "iotypes.inc" +#undef X + TYPE_UNKNOWN, +}; + +enum class IOSide +{ + LEFT, + RIGHT, + TOP, + BOTTOM, +}; + +std::string iotype_to_str(IOType type); +IOType ioType_from_str(const std::string &name); + +// IO related functions +IOVoltage get_vccio(IOType type); +bool is_strong_vccio_constraint(IOType type, PortType dir, IOSide side); +bool is_differential(IOType type); +bool is_referenced(IOType type); + +bool valid_loc_for_io(IOType type, PortType dir, IOSide side, int z); + +NEXTPNR_NAMESPACE_END + +#endif diff --git a/ecp5/iotypes.inc b/ecp5/iotypes.inc new file mode 100644 index 00000000..5984e79e --- /dev/null +++ b/ecp5/iotypes.inc @@ -0,0 +1,37 @@ +X(LVTTL33) +X(LVCMOS33) +X(LVCMOS25) +X(LVCMOS18) +X(LVCMOS15) +X(LVCMOS12) + +X(SSTL18_I) +X(SSTL18_II) +X(SSTL15_I) +X(SSTL15_II) +X(SSTL135_I) +X(SSTL135_II) +X(HSUL12) + +X(SSTL18D_I) +X(SSTL18D_II) +X(SSTL135D_I) +X(SSTL135D_II) +X(SSTL15D_I) +X(SSTL15D_II) +X(HSUL12D) +X(LVCMOS33D) +X(LVCMOS25D) + +X(LVDS) +X(BLVDS25) +X(MLVDS25) +X(LVPECL33) +X(SLVS) +X(SUBLVDS) +X(LVCMOS18D) + +X(LVDS25E) +X(BLVDS25E) +X(MLVDS25E) +X(LVPECL33E) diff --git a/ecp5/main.cc b/ecp5/main.cc index 5a4a900a..9f683a7b 100644 --- a/ecp5/main.cc +++ b/ecp5/main.cc @@ -63,6 +63,7 @@ int main(int argc, char *argv[]) #ifndef NO_GUI options.add_options()("gui", "start gui"); #endif + options.add_options()("test", "check architecture database integrity"); options.add_options()("25k", "set device type to LFE5U-25F"); options.add_options()("45k", "set device type to LFE5U-45F"); @@ -99,18 +100,16 @@ int main(int argc, char *argv[]) } if (vm.count("help") || argc == 1) { - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; std::cout << "\n"; std::cout << options << "\n"; return argc != 1; } if (vm.count("version")) { - std::cout << boost::filesystem::basename(argv[0]) - << " -- Next Generation Place and Route (git " - "sha1 " GIT_COMMIT_HASH_STR ")\n"; + std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git " + "sha1 " GIT_COMMIT_HASH_STR ")\n"; return 1; } @@ -148,6 +147,9 @@ int main(int argc, char *argv[]) if (vm.count("no-tmdriv")) ctx->timing_driven = false; + if (vm.count("test")) + ctx->archcheck(); + #ifndef NO_GUI if (vm.count("gui")) { Application a(argc, argv); @@ -165,8 +167,12 @@ int main(int argc, char *argv[]) if (!ctx->pack() && !ctx->force) log_error("Packing design failed.\n"); - if (vm.count("freq")) + if (vm.count("freq")) { ctx->target_freq = vm["freq"].as<double>() * 1e6; + ctx->user_freq = true; + } else { + log_warning("Target frequency not specified. Will optimise for max frequency.\n"); + } assign_budget(ctx.get()); ctx->check(); print_utilisation(ctx.get()); diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index b5cd53f1..cf12e775 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -10,11 +10,7 @@ type_at_location = dict() tiletype_names = dict() parser = argparse.ArgumentParser(description="import ECP5 routing and bels from Project Trellis") -group = parser.add_mutually_exclusive_group() -group.add_argument("-b", "--binary", action="store_true") -group.add_argument("-c", "--c_file", action="store_true") parser.add_argument("device", type=str, help="target device") -parser.add_argument("outfile", type=argparse.FileType('w'), help="output filename") parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc") args = parser.parse_args() @@ -36,284 +32,50 @@ portpins = dict() class BinaryBlobAssembler: - def __init__(self, cname, endianness, nodebug=False): - assert endianness in ["le", "be"] - self.cname = cname - self.endianness = endianness - self.finalized = False - self.data = bytearray() - self.comments = dict() - self.labels = dict() - self.exports = set() - self.labels_byaddr = dict() - self.ltypes_byaddr = dict() - self.strings = dict() - self.refs = dict() - self.nodebug = nodebug - - def l(self, name, ltype=None, export=False): - assert not self.finalized - assert name not in self.labels - assert len(self.data) not in self.labels_byaddr - self.labels[name] = len(self.data) - if ltype is not None: - self.ltypes_byaddr[len(self.data)] = ltype - self.labels_byaddr[len(self.data)] = name - if export: - assert ltype is not None - self.exports.add(len(self.data)) + def l(self, name, ltype = None, export = False): + if ltype is None: + print("label %s" % (name,)) + else: + print("label %s %s" % (name, ltype)) def r(self, name, comment): - assert not self.finalized - assert len(self.data) % 4 == 0 - assert len(self.data) not in self.refs - if self.nodebug: - comment = None - if name is not None: - self.refs[len(self.data)] = (name, comment) - self.data.append(0) - self.data.append(0) - self.data.append(0) - self.data.append(0) - if (name is None) and (comment is not None): - self.comments[len(self.data)] = comment + " (null reference)" + if comment is None: + print("ref %s" % (name,)) + else: + print("ref %s %s" % (name, comment)) def s(self, s, comment): - assert not self.finalized - if self.nodebug: - comment = None - if s not in self.strings: - index = len(self.strings) - self.strings[s] = index - else: - index = self.strings[s] - if comment is not None: - self.r("str%d" % index, '%s: "%s"' % (comment, s)) - else: - self.r("str%d" % index, None) + print("str %s" % s) def u8(self, v, comment): - assert not self.finalized - if self.nodebug: - comment = None - self.data.append(v) - if comment is not None: - self.comments[len(self.data)] = comment + if comment is None: + print("u8 %d" % (v,)) + else: + print("u8 %d %s" % (v, comment)) def u16(self, v, comment): - assert not self.finalized - assert len(self.data) % 2 == 0 - if self.nodebug: - comment = None - if self.endianness == "le": - self.data.append(v & 255) - self.data.append((v >> 8) & 255) - elif self.endianness == "be": - self.data.append((v >> 8) & 255) - self.data.append(v & 255) - else: - assert 0 - if comment is not None: - self.comments[len(self.data)] = comment - - def s16(self, v, comment): - assert not self.finalized - assert len(self.data) % 2 == 0 - if self.nodebug: - comment = None - c2val = (((-v) ^ 0xffff) + 1) if v < 0 else v - if self.endianness == "le": - self.data.append(c2val & 255) - self.data.append((c2val >> 8) & 255) - elif self.endianness == "be": - self.data.append((c2val >> 8) & 255) - self.data.append(c2val & 255) + if comment is None: + print("u16 %d" % (v,)) else: - assert 0 - if comment is not None: - self.comments[len(self.data)] = comment + print("u16 %d %s" % (v, comment)) def u32(self, v, comment): - assert not self.finalized - assert len(self.data) % 4 == 0 - if self.nodebug: - comment = None - if self.endianness == "le": - self.data.append(v & 255) - self.data.append((v >> 8) & 255) - self.data.append((v >> 16) & 255) - self.data.append((v >> 24) & 255) - elif self.endianness == "be": - self.data.append((v >> 24) & 255) - self.data.append((v >> 16) & 255) - self.data.append((v >> 8) & 255) - self.data.append(v & 255) + if comment is None: + print("u32 %d" % (v,)) else: - assert 0 - if comment is not None: - self.comments[len(self.data)] = comment - - def finalize(self): - assert not self.finalized - for s, index in sorted(self.strings.items()): - self.l("str%d" % index, "char") - for c in s: - self.data.append(ord(c)) - self.data.append(0) - self.finalized = True - cursor = 0 - while cursor < len(self.data): - if cursor in self.refs: - v = self.labels[self.refs[cursor][0]] - cursor - if self.endianness == "le": - self.data[cursor + 0] = (v & 255) - self.data[cursor + 1] = ((v >> 8) & 255) - self.data[cursor + 2] = ((v >> 16) & 255) - self.data[cursor + 3] = ((v >> 24) & 255) - elif self.endianness == "be": - self.data[cursor + 0] = ((v >> 24) & 255) - self.data[cursor + 1] = ((v >> 16) & 255) - self.data[cursor + 2] = ((v >> 8) & 255) - self.data[cursor + 3] = (v & 255) - else: - assert 0 - cursor += 4 - else: - cursor += 1 - - def write_verbose_c(self, f, ctype="const unsigned char"): - assert self.finalized - print("%s %s[%d] = {" % (ctype, self.cname, len(self.data)), file=f) - cursor = 0 - bytecnt = 0 - while cursor < len(self.data): - if cursor in self.comments: - if bytecnt == 0: - print(" ", end="", file=f) - print(" // %s" % self.comments[cursor], file=f) - bytecnt = 0 - if cursor in self.labels_byaddr: - if bytecnt != 0: - print(file=f) - if cursor in self.exports: - print("#define %s ((%s*)(%s+%d))" % ( - self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f) - else: - print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]), file=f) - bytecnt = 0 - if cursor in self.refs: - if bytecnt != 0: - print(file=f) - print(" ", end="", file=f) - print(" %-4s" % ("%d," % self.data[cursor + 0]), end="", file=f) - print(" %-4s" % ("%d," % self.data[cursor + 1]), end="", file=f) - print(" %-4s" % ("%d," % self.data[cursor + 2]), end="", file=f) - print(" %-4s" % ("%d," % self.data[cursor + 3]), end="", file=f) - print(" // [%d] %s (reference to %s)" % (cursor, self.refs[cursor][1], self.refs[cursor][0]), file=f) - bytecnt = 0 - cursor += 4 - else: - if bytecnt == 0: - print(" ", end="", file=f) - print(" %-4s" % ("%d," % self.data[cursor]), end=("" if bytecnt < 15 else "\n"), file=f) - bytecnt = (bytecnt + 1) & 15 - cursor += 1 - if bytecnt != 0: - print(file=f) - print("};", file=f) - - def write_compact_c(self, f, ctype="const unsigned char"): - assert self.finalized - print("%s %s[%d] = {" % (ctype, self.cname, len(self.data)), file=f) - column = 0 - for v in self.data: - if column == 0: - print(" ", end="", file=f) - column += 2 - s = "%d," % v - print(s, end="", file=f) - column += len(s) - if column > 75: - print(file=f) - column = 0 - if column != 0: - print(file=f) - for cursor in self.exports: - print("#define %s ((%s*)(%s+%d))" % ( - self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f) - print("};", file=f) - - def write_uint64_c(self, f, ctype="const uint64_t"): - assert self.finalized - print("%s %s[%d] = {" % (ctype, self.cname, (len(self.data) + 7) // 8), file=f) - column = 0 - for i in range((len(self.data) + 7) // 8): - v0 = self.data[8 * i + 0] if 8 * i + 0 < len(self.data) else 0 - v1 = self.data[8 * i + 1] if 8 * i + 1 < len(self.data) else 0 - v2 = self.data[8 * i + 2] if 8 * i + 2 < len(self.data) else 0 - v3 = self.data[8 * i + 3] if 8 * i + 3 < len(self.data) else 0 - v4 = self.data[8 * i + 4] if 8 * i + 4 < len(self.data) else 0 - v5 = self.data[8 * i + 5] if 8 * i + 5 < len(self.data) else 0 - v6 = self.data[8 * i + 6] if 8 * i + 6 < len(self.data) else 0 - v7 = self.data[8 * i + 7] if 8 * i + 7 < len(self.data) else 0 - if self.endianness == "le": - v = v0 << 0 - v |= v1 << 8 - v |= v2 << 16 - v |= v3 << 24 - v |= v4 << 32 - v |= v5 << 40 - v |= v6 << 48 - v |= v7 << 56 - elif self.endianness == "be": - v = v7 << 0 - v |= v6 << 8 - v |= v5 << 16 - v |= v4 << 24 - v |= v3 << 32 - v |= v2 << 40 - v |= v1 << 48 - v |= v0 << 56 - else: - assert 0 - if column == 3: - print(" 0x%016x," % v, file=f) - column = 0 - else: - if column == 0: - print(" ", end="", file=f) - print(" 0x%016x," % v, end="", file=f) - column += 1 - if column != 0: - print("", file=f) - print("};", file=f) - - def write_string_c(self, f, ctype="const char"): - assert self.finalized - assert self.data[len(self.data) - 1] == 0 - print("%s %s[%d] =" % (ctype, self.cname, len(self.data)), file=f) - print(" \"", end="", file=f) - column = 0 - for i in range(len(self.data) - 1): - if (self.data[i] < 32) or (self.data[i] > 126): - print("\\%03o" % self.data[i], end="", file=f) - column += 4 - elif self.data[i] == ord('"') or self.data[i] == ord('\\'): - print("\\" + chr(self.data[i]), end="", file=f) - column += 2 - else: - print(chr(self.data[i]), end="", file=f) - column += 1 - if column > 70 and (i != len(self.data) - 2): - print("\"\n \"", end="", file=f) - column = 0 - print("\";", file=f) + print("u32 %d %s" % (v, comment)) + + def pre(self, s): + print("pre %s" % s) - def write_binary(self, f): - assert self.finalized - assert self.data[len(self.data) - 1] == 0 - f.buffer.write(self.data) + def post(self, s): + print("post %s" % s) + def push(self, name): + print("push %s" % name) + + def pop(self): + print("pop") bel_types = { "NONE": 0, @@ -364,13 +126,25 @@ def process_pio_db(ddrg, device): if bel_idx is not None: pindata.append((loc, bel_idx, bank, pinfunc)) +global_data = {} +quadrants = ["UL", "UR", "LL", "LR"] +def process_loc_globals(chip): + for y in range(0, max_row+1): + for x in range(0, max_col+1): + quad = chip.global_data.get_quadrant(y, x) + tapdrv = chip.global_data.get_tap_driver(y, x) + global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col) def write_database(dev_name, ddrg, endianness): def write_loc(loc, sym_name): - bba.s16(loc.x, "%s.x" % sym_name) - bba.s16(loc.y, "%s.y" % sym_name) - - bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness) + bba.u16(loc.x, "%s.x" % sym_name) + bba.u16(loc.y, "%s.y" % sym_name) + + bba = BinaryBlobAssembler() + bba.pre('#include "nextpnr.h"') + bba.pre('NEXTPNR_NAMESPACE_BEGIN') + bba.post('NEXTPNR_NAMESPACE_END') + bba.push("chipdb_blob_%s" % dev_name) bba.r("chip_info", "chip_info") loctypes = list([_.key() for _ in ddrg.locationTypes]) @@ -450,6 +224,14 @@ def write_database(dev_name, ddrg, endianness): for y in range(0, max_row+1): for x in range(0, max_col+1): bba.u32(loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)]), "loctype") + + bba.l("location_glbinfo", "GlobalInfoPOD") + for y in range(0, max_row+1): + for x in range(0, max_col+1): + bba.u16(global_data[x, y][2], "tap_col") + bba.u8(global_data[x, y][1], "tap_dir") + bba.u8(global_data[x, y][0], "quad") + for package, pkgdata in sorted(packages.items()): bba.l("package_data_%s" % package, "PackagePinPOD") for pin in pkgdata: @@ -491,11 +273,12 @@ def write_database(dev_name, ddrg, endianness): bba.r("locations", "locations") bba.r("location_types", "location_type") + bba.r("location_glbinfo", "location_glbinfo") bba.r("tiletype_names", "tiletype_names") bba.r("package_data", "package_info") bba.r("pio_info", "pio_info") - bba.finalize() + bba.pop() return bba dev_names = {"25k": "LFE5U-25F", "45k": "LFE5U-45F", "85k": "LFE5U-85F"} @@ -518,30 +301,18 @@ def main(): idx = len(portpins) + 1 portpins[line[1]] = idx - print("Initialising chip...") + # print("Initialising chip...") chip = pytrellis.Chip(dev_names[args.device]) - print("Building routing graph...") + # print("Building routing graph...") ddrg = pytrellis.make_dedup_chipdb(chip) max_row = chip.get_max_row() max_col = chip.get_max_col() process_pio_db(ddrg, args.device) - print("{} unique location types".format(len(ddrg.locationTypes))) + process_loc_globals(chip) + # print("{} unique location types".format(len(ddrg.locationTypes))) bba = write_database(args.device, ddrg, "le") - if args.c_file: - print('#include "nextpnr.h"', file=args.outfile) - print('NEXTPNR_NAMESPACE_BEGIN', file=args.outfile) - - - if args.binary: - bba.write_binary(args.outfile) - - if args.c_file: - bba.write_string_c(args.outfile) - - if args.c_file: - print('NEXTPNR_NAMESPACE_END', file=args.outfile) if __name__ == "__main__": main() |