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-rw-r--r--common/nextpnr.h23
1 files changed, 13 insertions, 10 deletions
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 0a501910..c2fe5192 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -575,6 +575,7 @@ struct DelayPair
struct DelayQuad
{
DelayPair rise, fall;
+ DelayQuad(){};
explicit DelayQuad(delay_t delay) : rise(delay), fall(delay){};
DelayQuad(delay_t min_delay, delay_t max_delay) : rise(min_delay, max_delay), fall(min_delay, max_delay){};
DelayQuad(DelayPair rise, DelayPair fall) : rise(rise), fall(fall){};
@@ -588,6 +589,8 @@ struct DelayQuad
delay_t minDelay() const { return std::min<delay_t>(rise.minDelay(), fall.minDelay()); };
delay_t maxDelay() const { return std::max<delay_t>(rise.maxDelay(), fall.maxDelay()); };
+ DelayPair delayPair() const { return DelayPair(minDelay(), maxDelay()); };
+
DelayQuad operator+(const DelayQuad &other) const { return {rise + other.rise, fall + other.fall}; }
};
@@ -686,15 +689,15 @@ struct TimingClockingInfo
{
IdString clock_port; // Port name of clock domain
ClockEdge edge;
- DelayInfo setup, hold; // Input timing checks
- DelayInfo clockToQ; // Output clock-to-Q time
+ DelayPair setup, hold; // Input timing checks
+ DelayQuad clockToQ; // Output clock-to-Q time
};
struct ClockConstraint
{
- DelayInfo high;
- DelayInfo low;
- DelayInfo period;
+ DelayPair high;
+ DelayPair low;
+ DelayPair period;
TimingConstrObjectId domain_tmg_id;
};
@@ -1152,7 +1155,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual NetInfo *getBoundWireNet(WireId wire) const = 0;
virtual WireId getConflictingWireWire(WireId wire) const = 0;
virtual NetInfo *getConflictingWireNet(WireId wire) const = 0;
- virtual DelayInfo getWireDelay(WireId wire) const = 0;
+ virtual DelayQuad getWireDelay(WireId wire) const = 0;
// Pip methods
virtual typename R::AllPipsRangeT getPips() const = 0;
virtual PipId getPipByName(IdStringList name) const = 0;
@@ -1168,7 +1171,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual NetInfo *getConflictingPipNet(PipId pip) const = 0;
virtual WireId getPipSrcWire(PipId pip) const = 0;
virtual WireId getPipDstWire(PipId pip) const = 0;
- virtual DelayInfo getPipDelay(PipId pip) const = 0;
+ virtual DelayQuad getPipDelay(PipId pip) const = 0;
virtual Loc getPipLocation(PipId pip) const = 0;
// Group methods
virtual GroupId getGroupByName(IdStringList name) const = 0;
@@ -1183,7 +1186,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual delay_t getDelayEpsilon() const = 0;
virtual delay_t getRipupDelayPenalty() const = 0;
virtual float getDelayNS(delay_t v) const = 0;
- virtual DelayInfo getDelayFromNS(float ns) const = 0;
+ virtual delay_t getDelayFromNS(float ns) const = 0;
virtual uint32_t getDelayChecksum(delay_t v) const = 0;
virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
@@ -1195,7 +1198,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual DecalXY getPipDecal(PipId pip) const = 0;
virtual DecalXY getGroupDecal(GroupId group) const = 0;
// Cell timing methods
- virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const = 0;
+ virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const = 0;
virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const = 0;
virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const = 0;
// Placement validity checks
@@ -1426,7 +1429,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
virtual DecalXY getGroupDecal(GroupId group) const override { return DecalXY(); }
// Cell timing methods
- virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override
+ virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override
{
return false;
}