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-rw-r--r--common/design.h4
-rw-r--r--common/nextpnr.cc2
-rw-r--r--common/place_sa.cc8
-rw-r--r--common/pybindings.cc2
-rw-r--r--dummy/chip.cc80
-rw-r--r--dummy/chip.h8
-rw-r--r--dummy/main.cc2
-rw-r--r--dummy/pybindings.cc2
-rw-r--r--ice40/arch_place.cc4
-rw-r--r--ice40/bitstream.cc42
-rw-r--r--ice40/chip.cc56
-rw-r--r--ice40/chip.h13
-rw-r--r--ice40/main.cc32
-rw-r--r--ice40/pybindings.cc62
14 files changed, 158 insertions, 159 deletions
diff --git a/common/design.h b/common/design.h
index e763ed48..13c66d4e 100644
--- a/common/design.h
+++ b/common/design.h
@@ -72,9 +72,9 @@ struct CellInfo
struct Design
{
- struct Chip chip;
+ struct Arch chip;
- Design(ChipArgs args) : chip(args)
+ Design(ArchArgs args) : chip(args)
{
// ...
}
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index d177fe71..374a5edb 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -35,7 +35,7 @@ void IdString::initialize()
void IdString::initialize_add(const char *s, int idx)
{
assert(database_str_to_idx->count(s) == 0);
- assert(database_idx_to_str->size() == idx);
+ assert(int(database_idx_to_str->size()) == idx);
auto insert_rc = database_str_to_idx->insert({s, idx});
database_idx_to_str->push_back(&insert_rc.first->first);
}
diff --git a/common/place_sa.cc b/common/place_sa.cc
index 25297d31..f1c3dea2 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -78,7 +78,7 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
BelId best_bel = BelId();
float best_score = std::numeric_limits<float>::infinity(),
best_ripup_score = std::numeric_limits<float>::infinity();
- Chip &chip = design->chip;
+ Arch &chip = design->chip;
CellInfo *ripup_target = nullptr;
BelId ripup_bel = BelId();
if (cell->bel != BelId()) {
@@ -141,7 +141,7 @@ struct SAState
};
// Get the total estimated wirelength for a net
-static float get_wirelength(Chip *chip, NetInfo *net)
+static float get_wirelength(Arch *chip, NetInfo *net)
{
float wirelength = 0;
int driver_x = 0, driver_y = 0;
@@ -181,7 +181,7 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
static std::vector<std::pair<NetInfo *, float>> new_lengths;
new_lengths.clear();
update.clear();
- Chip &chip = design->chip;
+ Arch &chip = design->chip;
BelId oldBel = cell->bel;
IdString other = chip.getBelCell(newBel, true);
CellInfo *other_cell = nullptr;
@@ -264,7 +264,7 @@ swap_fail:
BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
rnd_state &rnd)
{
- Chip &chip = design->chip;
+ Arch &chip = design->chip;
BelType targetType = belTypeFromId(cell->type);
int x = 0, y = 0;
chip.estimatePosition(cell->bel, x, y);
diff --git a/common/pybindings.cc b/common/pybindings.cc
index 89f98716..3621d27a 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -57,7 +57,7 @@ void parse_json_shim(std::string filename, Design &d)
}
// Create a new Chip and load design from json file
-Design load_design_shim(std::string filename, ChipArgs args)
+Design load_design_shim(std::string filename, ArchArgs args)
{
Design d(args);
parse_json_shim(filename, d);
diff --git a/dummy/chip.cc b/dummy/chip.cc
index 965517fe..5bbf36e3 100644
--- a/dummy/chip.cc
+++ b/dummy/chip.cc
@@ -22,48 +22,48 @@
NEXTPNR_NAMESPACE_BEGIN
-Chip::Chip(ChipArgs) {}
+Arch::Arch(ArchArgs) {}
-std::string Chip::getChipName() { return "Dummy"; }
+std::string Arch::getChipName() { return "Dummy"; }
void IdString::initialize_chip() {}
// ---------------------------------------------------------------
-BelId Chip::getBelByName(IdString name) const { return BelId(); }
+BelId Arch::getBelByName(IdString name) const { return BelId(); }
-IdString Chip::getBelName(BelId bel) const { return IdString(); }
+IdString Arch::getBelName(BelId bel) const { return IdString(); }
-void Chip::bindBel(BelId bel, IdString cell) {}
+void Arch::bindBel(BelId bel, IdString cell) {}
-void Chip::unbindBel(BelId bel) {}
+void Arch::unbindBel(BelId bel) {}
-bool Chip::checkBelAvail(BelId bel) const { return false; }
+bool Arch::checkBelAvail(BelId bel) const { return false; }
-IdString Chip::getBelCell(BelId bel, bool conflicting) const
+IdString Arch::getBelCell(BelId bel, bool conflicting) const
{
return IdString();
}
-const std::vector<BelId> &Chip::getBels() const
+const std::vector<BelId> &Arch::getBels() const
{
static std::vector<BelId> ret;
return ret;
}
-const std::vector<BelId> &Chip::getBelsByType(BelType type) const
+const std::vector<BelId> &Arch::getBelsByType(BelType type) const
{
static std::vector<BelId> ret;
return ret;
}
-BelType Chip::getBelType(BelId bel) const { return BelType(); }
+BelType Arch::getBelType(BelId bel) const { return BelType(); }
-WireId Chip::getWireBelPin(BelId bel, PortPin pin) const { return WireId(); }
+WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { return WireId(); }
-BelPin Chip::getBelPinUphill(WireId wire) const { return BelPin(); }
+BelPin Arch::getBelPinUphill(WireId wire) const { return BelPin(); }
-const std::vector<BelPin> &Chip::getBelPinsDownhill(WireId wire) const
+const std::vector<BelPin> &Arch::getBelPinsDownhill(WireId wire) const
{
static std::vector<BelPin> ret;
return ret;
@@ -71,22 +71,22 @@ const std::vector<BelPin> &Chip::getBelPinsDownhill(WireId wire) const
// ---------------------------------------------------------------
-WireId Chip::getWireByName(IdString name) const { return WireId(); }
+WireId Arch::getWireByName(IdString name) const { return WireId(); }
-IdString Chip::getWireName(WireId wire) const { return IdString(); }
+IdString Arch::getWireName(WireId wire) const { return IdString(); }
-void Chip::bindWire(WireId wire, IdString net) {}
+void Arch::bindWire(WireId wire, IdString net) {}
-void Chip::unbindWire(WireId wire) {}
+void Arch::unbindWire(WireId wire) {}
-bool Chip::checkWireAvail(WireId wire) const { return false; }
+bool Arch::checkWireAvail(WireId wire) const { return false; }
-IdString Chip::getWireNet(WireId wire, bool conflicting) const
+IdString Arch::getWireNet(WireId wire, bool conflicting) const
{
return IdString();
}
-const std::vector<WireId> &Chip::getWires() const
+const std::vector<WireId> &Arch::getWires() const
{
static std::vector<WireId> ret;
return ret;
@@ -94,46 +94,46 @@ const std::vector<WireId> &Chip::getWires() const
// ---------------------------------------------------------------
-PipId Chip::getPipByName(IdString name) const { return PipId(); }
+PipId Arch::getPipByName(IdString name) const { return PipId(); }
-IdString Chip::getPipName(PipId pip) const { return IdString(); }
+IdString Arch::getPipName(PipId pip) const { return IdString(); }
-void Chip::bindPip(PipId pip, IdString net) {}
+void Arch::bindPip(PipId pip, IdString net) {}
-void Chip::unbindPip(PipId pip) {}
+void Arch::unbindPip(PipId pip) {}
-bool Chip::checkPipAvail(PipId pip) const { return false; }
+bool Arch::checkPipAvail(PipId pip) const { return false; }
-IdString Chip::getPipNet(PipId pip, bool conflicting) const
+IdString Arch::getPipNet(PipId pip, bool conflicting) const
{
return IdString();
}
-const std::vector<PipId> &Chip::getPips() const
+const std::vector<PipId> &Arch::getPips() const
{
static std::vector<PipId> ret;
return ret;
}
-WireId Chip::getPipSrcWire(PipId pip) const { return WireId(); }
+WireId Arch::getPipSrcWire(PipId pip) const { return WireId(); }
-WireId Chip::getPipDstWire(PipId pip) const { return WireId(); }
+WireId Arch::getPipDstWire(PipId pip) const { return WireId(); }
-DelayInfo Chip::getPipDelay(PipId pip) const { return DelayInfo(); }
+DelayInfo Arch::getPipDelay(PipId pip) const { return DelayInfo(); }
-const std::vector<PipId> &Chip::getPipsDownhill(WireId wire) const
+const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const
{
static std::vector<PipId> ret;
return ret;
}
-const std::vector<PipId> &Chip::getPipsUphill(WireId wire) const
+const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const
{
static std::vector<PipId> ret;
return ret;
}
-const std::vector<PipId> &Chip::getWireAliases(WireId wire) const
+const std::vector<PipId> &Arch::getWireAliases(WireId wire) const
{
static std::vector<PipId> ret;
return ret;
@@ -141,36 +141,36 @@ const std::vector<PipId> &Chip::getWireAliases(WireId wire) const
// ---------------------------------------------------------------
-bool Chip::estimatePosition(BelId bel, int &x, int &y) const
+bool Arch::estimatePosition(BelId bel, int &x, int &y) const
{
x = 0.0;
y = 0.0;
return false;
}
-delay_t Chip::estimateDelay(WireId src, WireId dst) const { return 0.0; }
+delay_t Arch::estimateDelay(WireId src, WireId dst) const { return 0.0; }
// ---------------------------------------------------------------
-std::vector<GraphicElement> Chip::getFrameGraphics() const
+std::vector<GraphicElement> Arch::getFrameGraphics() const
{
static std::vector<GraphicElement> ret;
return ret;
}
-std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
+std::vector<GraphicElement> Arch::getBelGraphics(BelId bel) const
{
static std::vector<GraphicElement> ret;
return ret;
}
-std::vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
+std::vector<GraphicElement> Arch::getWireGraphics(WireId wire) const
{
static std::vector<GraphicElement> ret;
return ret;
}
-std::vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
+std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
{
static std::vector<GraphicElement> ret;
return ret;
diff --git a/dummy/chip.h b/dummy/chip.h
index 03e16e64..c0803510 100644
--- a/dummy/chip.h
+++ b/dummy/chip.h
@@ -63,15 +63,13 @@ struct BelPin
PortPin pin;
};
-struct ChipArgs
+struct ArchArgs
{
};
-std::string getChipName(ChipArgs id);
-
-struct Chip
+struct Arch
{
- Chip(ChipArgs args);
+ Arch(ArchArgs args);
std::string getChipName();
diff --git a/dummy/main.cc b/dummy/main.cc
index 7aa2f08f..9ac4db26 100644
--- a/dummy/main.cc
+++ b/dummy/main.cc
@@ -27,7 +27,7 @@ USING_NEXTPNR_NAMESPACE
int main(int argc, char *argv[])
{
- Design design(ChipArgs{});
+ Design design(ArchArgs{});
QApplication a(argc, argv);
MainWindow w(&design);
diff --git a/dummy/pybindings.cc b/dummy/pybindings.cc
index ec0e20b2..87716267 100644
--- a/dummy/pybindings.cc
+++ b/dummy/pybindings.cc
@@ -23,6 +23,6 @@
NEXTPNR_NAMESPACE_BEGIN
-void arch_wrap_python() { class_<ChipArgs>("ChipArgs"); }
+void arch_wrap_python() { class_<ArchArgs>("ArchArgs"); }
NEXTPNR_NAMESPACE_END
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 3205fb6e..d9210378 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -90,7 +90,7 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
bool isBelLocationValid(Design *design, BelId bel)
{
- const Chip &chip = design->chip;
+ const Arch &chip = design->chip;
if (chip.getBelType(bel) == TYPE_ICESTORM_LC) {
std::vector<const CellInfo *> cells;
for (auto bel_other : chip.getBelsAtSameTile(bel)) {
@@ -112,7 +112,7 @@ bool isBelLocationValid(Design *design, BelId bel)
bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
{
- const Chip &chip = design->chip;
+ const Arch &chip = design->chip;
if (cell->type == "ICESTORM_LC") {
assert(chip.getBelType(bel) == TYPE_ICESTORM_LC);
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 4991df5e..ff839ba1 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -23,7 +23,7 @@
NEXTPNR_NAMESPACE_BEGIN
-inline TileType tile_at(const Chip &chip, int x, int y)
+inline TileType tile_at(const Arch &chip, int x, int y)
{
return chip.chip_info->tile_grid[y * chip.chip_info->width + x];
}
@@ -97,7 +97,7 @@ char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
void write_asc(const Design &design, std::ostream &out)
{
- const Chip &chip = design.chip;
+ const Arch &chip = design.chip;
// [y][x][row][col]
const ChipInfoPOD &ci = *chip.chip_info;
const BitstreamInfoPOD &bi = *ci.bits_info;
@@ -115,18 +115,18 @@ void write_asc(const Design &design, std::ostream &out)
out << ".comment from next-pnr" << std::endl;
switch (chip.args.type) {
- case ChipArgs::LP384:
+ case ArchArgs::LP384:
out << ".device 384" << std::endl;
break;
- case ChipArgs::HX1K:
- case ChipArgs::LP1K:
+ case ArchArgs::HX1K:
+ case ArchArgs::LP1K:
out << ".device 1k" << std::endl;
break;
- case ChipArgs::HX8K:
- case ChipArgs::LP8K:
+ case ArchArgs::HX8K:
+ case ArchArgs::LP8K:
out << ".device 8k" << std::endl;
break;
- case ChipArgs::UP5K:
+ case ArchArgs::UP5K:
out << ".device 5k" << std::endl;
break;
default:
@@ -213,8 +213,8 @@ void write_asc(const Design &design, std::ostream &out)
input_en = true;
}
- if (chip.args.type == ChipArgs::LP1K ||
- chip.args.type == ChipArgs::HX1K) {
+ if (chip.args.type == ArchArgs::LP1K ||
+ chip.args.type == ArchArgs::HX1K) {
set_config(ti, config.at(iey).at(iex),
"IoCtrl.IE_" + std::to_string(iez), !input_en);
set_config(ti, config.at(iey).at(iex),
@@ -232,8 +232,8 @@ void write_asc(const Design &design, std::ostream &out)
int x = beli.x, y = beli.y;
const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB];
- if (!(chip.args.type == ChipArgs::LP1K ||
- chip.args.type == ChipArgs::HX1K)) {
+ if (!(chip.args.type == ArchArgs::LP1K ||
+ chip.args.type == ArchArgs::HX1K)) {
set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp",
true);
}
@@ -268,8 +268,8 @@ void write_asc(const Design &design, std::ostream &out)
int iex, iey, iez;
std::tie(iex, iey, iez) = ieren;
if (iez != -1) {
- if (chip.args.type == ChipArgs::LP1K ||
- chip.args.type == ChipArgs::HX1K) {
+ if (chip.args.type == ArchArgs::LP1K ||
+ chip.args.type == ArchArgs::HX1K) {
set_config(ti, config.at(iey).at(iex),
"IoCtrl.IE_" + std::to_string(iez), true);
set_config(ti, config.at(iey).at(iex),
@@ -281,8 +281,8 @@ void write_asc(const Design &design, std::ostream &out)
const BelInfoPOD &beli = ci.bel_data[bel.index];
int x = beli.x, y = beli.y;
const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
- if ((chip.args.type == ChipArgs::LP1K ||
- chip.args.type == ChipArgs::HX1K)) {
+ if ((chip.args.type == ArchArgs::LP1K ||
+ chip.args.type == ArchArgs::HX1K)) {
set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
}
}
@@ -296,17 +296,17 @@ void write_asc(const Design &design, std::ostream &out)
// set all ColBufCtrl bits (FIXME)
bool setColBufCtrl = true;
- if (chip.args.type == ChipArgs::LP1K ||
- chip.args.type == ChipArgs::HX1K) {
+ if (chip.args.type == ArchArgs::LP1K ||
+ chip.args.type == ArchArgs::HX1K) {
if (tile == TILE_RAMB || tile == TILE_RAMT) {
setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13);
} else {
setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13);
}
- } else if (chip.args.type == ChipArgs::LP8K ||
- chip.args.type == ChipArgs::HX8K) {
+ } else if (chip.args.type == ArchArgs::LP8K ||
+ chip.args.type == ArchArgs::HX8K) {
setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
- } else if (chip.args.type == ChipArgs::UP5K) {
+ } else if (chip.args.type == ArchArgs::UP5K) {
if (tile == TILE_LOGIC) {
setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 ||
y == 26 || y == 27);
diff --git a/ice40/chip.cc b/ice40/chip.cc
index 7074070e..b269a3e3 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -78,10 +78,10 @@ PortPin portPinFromId(IdString id)
// -----------------------------------------------------------------------
-Chip::Chip(ChipArgs args) : args(args)
+Arch::Arch(ArchArgs args) : args(args)
{
#ifdef ICE40_HX1K_ONLY
- if (args.type == ChipArgs::HX1K) {
+ if (args.type == ArchArgs::HX1K) {
chip_info =
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)
->get();
@@ -89,19 +89,19 @@ Chip::Chip(ChipArgs args) : args(args)
log_error("Unsupported iCE40 chip type.\n");
}
#else
- if (args.type == ChipArgs::LP384) {
+ if (args.type == ArchArgs::LP384) {
chip_info =
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384)
->get();
- } else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
+ } else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
chip_info =
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)
->get();
- } else if (args.type == ChipArgs::UP5K) {
+ } else if (args.type == ArchArgs::UP5K) {
chip_info =
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k)
->get();
- } else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
+ } else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
chip_info =
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k)
->get();
@@ -128,26 +128,26 @@ Chip::Chip(ChipArgs args) : args(args)
// -----------------------------------------------------------------------
-std::string Chip::getChipName()
+std::string Arch::getChipName()
{
#ifdef ICE40_HX1K_ONLY
- if (args.type == ChipArgs::HX1K) {
+ if (args.type == ArchArgs::HX1K) {
return "Lattice LP1K";
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
- if (args.type == ChipArgs::LP384) {
+ if (args.type == ArchArgs::LP384) {
return "Lattice LP384";
- } else if (args.type == ChipArgs::LP1K) {
+ } else if (args.type == ArchArgs::LP1K) {
return "Lattice LP1K";
- } else if (args.type == ChipArgs::HX1K) {
+ } else if (args.type == ArchArgs::HX1K) {
return "Lattice HX1K";
- } else if (args.type == ChipArgs::UP5K) {
+ } else if (args.type == ArchArgs::UP5K) {
return "Lattice UP5K";
- } else if (args.type == ChipArgs::LP8K) {
+ } else if (args.type == ArchArgs::LP8K) {
return "Lattice LP8K";
- } else if (args.type == ChipArgs::HX8K) {
+ } else if (args.type == ArchArgs::HX8K) {
return "Lattice HX8K";
} else {
log_error("Unknown chip\n");
@@ -157,7 +157,7 @@ std::string Chip::getChipName()
// -----------------------------------------------------------------------
-BelId Chip::getBelByName(IdString name) const
+BelId Arch::getBelByName(IdString name) const
{
BelId ret;
@@ -173,7 +173,7 @@ BelId Chip::getBelByName(IdString name) const
return ret;
}
-BelRange Chip::getBelsAtSameTile(BelId bel) const
+BelRange Arch::getBelsAtSameTile(BelId bel) const
{
BelRange br;
assert(bel != BelId());
@@ -193,7 +193,7 @@ BelRange Chip::getBelsAtSameTile(BelId bel) const
return br;
}
-WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
+WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
{
WireId ret;
@@ -214,7 +214,7 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
// -----------------------------------------------------------------------
-WireId Chip::getWireByName(IdString name) const
+WireId Arch::getWireByName(IdString name) const
{
WireId ret;
@@ -232,7 +232,7 @@ WireId Chip::getWireByName(IdString name) const
// -----------------------------------------------------------------------
-PipId Chip::getPipByName(IdString name) const
+PipId Arch::getPipByName(IdString name) const
{
PipId ret;
@@ -251,7 +251,7 @@ PipId Chip::getPipByName(IdString name) const
return ret;
}
-IdString Chip::getPipName(PipId pip) const
+IdString Arch::getPipName(PipId pip) const
{
assert(pip != PipId());
@@ -272,7 +272,7 @@ IdString Chip::getPipName(PipId pip) const
// -----------------------------------------------------------------------
-BelId Chip::getPackagePinBel(const std::string &pin) const
+BelId Arch::getPackagePinBel(const std::string &pin) const
{
for (int i = 0; i < package_info->num_pins; i++) {
if (package_info->pins[i].name.get() == pin) {
@@ -284,7 +284,7 @@ BelId Chip::getPackagePinBel(const std::string &pin) const
return BelId();
}
-std::string Chip::getBelPackagePin(BelId bel) const
+std::string Arch::getBelPackagePin(BelId bel) const
{
for (int i = 0; i < package_info->num_pins; i++) {
if (package_info->pins[i].bel_index == bel.index) {
@@ -295,7 +295,7 @@ std::string Chip::getBelPackagePin(BelId bel) const
}
// -----------------------------------------------------------------------
-bool Chip::estimatePosition(BelId bel, int &x, int &y) const
+bool Arch::estimatePosition(BelId bel, int &x, int &y) const
{
assert(bel != BelId());
x = chip_info->bel_data[bel.index].x;
@@ -304,7 +304,7 @@ bool Chip::estimatePosition(BelId bel, int &x, int &y) const
return chip_info->bel_data[bel.index].type != TYPE_SB_GB;
}
-delay_t Chip::estimateDelay(WireId src, WireId dst) const
+delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
assert(src != WireId());
delay_t x1 = chip_info->wire_data[src.index].x;
@@ -319,7 +319,7 @@ delay_t Chip::estimateDelay(WireId src, WireId dst) const
// -----------------------------------------------------------------------
-std::vector<GraphicElement> Chip::getFrameGraphics() const
+std::vector<GraphicElement> Arch::getFrameGraphics() const
{
std::vector<GraphicElement> ret;
@@ -336,7 +336,7 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
return ret;
}
-std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
+std::vector<GraphicElement> Arch::getBelGraphics(BelId bel) const
{
std::vector<GraphicElement> ret;
@@ -402,14 +402,14 @@ std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
return ret;
}
-std::vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
+std::vector<GraphicElement> Arch::getWireGraphics(WireId wire) const
{
std::vector<GraphicElement> ret;
// FIXME
return ret;
}
-std::vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
+std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
{
std::vector<GraphicElement> ret;
// FIXME
diff --git a/ice40/chip.h b/ice40/chip.h
index d3eb7c70..8ba42290 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -443,7 +443,7 @@ struct PipRange
// -----------------------------------------------------------------------
-struct ChipArgs
+struct ArchArgs
{
enum
{
@@ -458,7 +458,7 @@ struct ChipArgs
std::string package;
};
-struct Chip
+struct Arch
{
const ChipInfoPOD *chip_info;
const PackageInfoPOD *package_info;
@@ -471,13 +471,14 @@ struct Chip
std::vector<IdString> wire_to_net;
std::vector<IdString> pip_to_net;
std::vector<IdString> switches_locked;
- Chip(ChipArgs args);
- ChipArgs args;
- // -------------------------------------------------
+ ArchArgs args;
+ Arch(ArchArgs args);
std::string getChipName();
+ // -------------------------------------------------
+
BelId getBelByName(IdString name) const;
IdString getBelName(BelId bel) const
@@ -641,7 +642,7 @@ struct Chip
bool checkPipAvail(PipId pip) const
{
assert(pip != PipId());
- if (args.type == ChipArgs::UP5K) {
+ if (args.type == ArchArgs::UP5K) {
int x = chip_info->pip_data[pip.index].x;
if (x == 0 || x == (chip_info->width - 1))
return false;
diff --git a/ice40/main.cc b/ice40/main.cc
index c43bffa7..ed660069 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -134,56 +134,56 @@ int main(int argc, char *argv[])
verbose = true;
}
- ChipArgs chipArgs;
+ ArchArgs chipArgs;
if (vm.count("lp384")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::LP384;
+ chipArgs.type = ArchArgs::LP384;
chipArgs.package = "qn32";
}
if (vm.count("lp1k")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::LP1K;
+ chipArgs.type = ArchArgs::LP1K;
chipArgs.package = "tq144";
}
if (vm.count("lp8k")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::LP8K;
+ chipArgs.type = ArchArgs::LP8K;
chipArgs.package = "ct256";
}
if (vm.count("hx1k")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::HX1K;
+ chipArgs.type = ArchArgs::HX1K;
chipArgs.package = "tq144";
}
if (vm.count("hx8k")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::HX8K;
+ chipArgs.type = ArchArgs::HX8K;
chipArgs.package = "ct256";
}
if (vm.count("up5k")) {
- if (chipArgs.type != ChipArgs::NONE)
+ if (chipArgs.type != ArchArgs::NONE)
goto help;
- chipArgs.type = ChipArgs::UP5K;
+ chipArgs.type = ArchArgs::UP5K;
chipArgs.package = "sg48";
}
- if (chipArgs.type == ChipArgs::NONE) {
- chipArgs.type = ChipArgs::HX1K;
+ if (chipArgs.type == ArchArgs::NONE) {
+ chipArgs.type = ArchArgs::HX1K;
chipArgs.package = "tq144";
}
#ifdef ICE40_HX1K_ONLY
- if (chipArgs.type != ChipArgs::HX1K) {
+ if (chipArgs.type != ArchArgs::HX1K) {
std::cout << "This version of nextpnr-ice40 is built with HX1K-support "
"only.\n";
return 1;
diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc
index c161949b..6ce35583 100644
--- a/ice40/pybindings.cc
+++ b/ice40/pybindings.cc
@@ -25,16 +25,16 @@ NEXTPNR_NAMESPACE_BEGIN
void arch_wrap_python()
{
- class_<ChipArgs>("ChipArgs").def_readwrite("type", &ChipArgs::type);
+ class_<ArchArgs>("ArchArgs").def_readwrite("type", &ArchArgs::type);
- enum_<decltype(std::declval<ChipArgs>().type)>("iCE40Type")
- .value("NONE", ChipArgs::NONE)
- .value("LP384", ChipArgs::LP384)
- .value("LP1K", ChipArgs::LP1K)
- .value("LP8K", ChipArgs::LP8K)
- .value("HX1K", ChipArgs::HX1K)
- .value("HX8K", ChipArgs::HX8K)
- .value("UP5K", ChipArgs::UP5K)
+ enum_<decltype(std::declval<ArchArgs>().type)>("iCE40Type")
+ .value("NONE", ArchArgs::NONE)
+ .value("LP384", ArchArgs::LP384)
+ .value("LP1K", ArchArgs::LP1K)
+ .value("LP8K", ArchArgs::LP8K)
+ .value("HX1K", ArchArgs::HX1K)
+ .value("HX8K", ArchArgs::HX8K)
+ .value("UP5K", ArchArgs::UP5K)
.export_values();
class_<BelId>("BelId").def_readwrite("index", &BelId::index);
@@ -53,28 +53,28 @@ void arch_wrap_python()
;
#undef X
- class_<Chip>("Chip", init<ChipArgs>())
- .def("getBelByName", &Chip::getBelByName)
- .def("getWireByName", &Chip::getWireByName)
- .def("getBelName", &Chip::getBelName)
- .def("getWireName", &Chip::getWireName)
- .def("getBels", &Chip::getBels)
- .def("getBelType", &Chip::getBelType)
- .def("getWireBelPin", &Chip::getWireBelPin)
- .def("getBelPinUphill", &Chip::getBelPinUphill)
- .def("getBelPinsDownhill", &Chip::getBelPinsDownhill)
- .def("getWires", &Chip::getWires)
- .def("getPipByName", &Chip::getPipByName)
- .def("getPipName", &Chip::getPipName)
- .def("getPips", &Chip::getPips)
- .def("getPipSrcWire", &Chip::getPipSrcWire)
- .def("getPipDstWire", &Chip::getPipDstWire)
- .def("getPipDelay", &Chip::getPipDelay)
- .def("getPipsDownhill", &Chip::getPipsDownhill)
- .def("getPipsUphill", &Chip::getPipsUphill)
- .def("getWireAliases", &Chip::getWireAliases)
- .def("estimatePosition", &Chip::estimatePosition)
- .def("estimateDelay", &Chip::estimateDelay);
+ class_<Arch>("Arch", init<ArchArgs>())
+ .def("getBelByName", &Arch::getBelByName)
+ .def("getWireByName", &Arch::getWireByName)
+ .def("getBelName", &Arch::getBelName)
+ .def("getWireName", &Arch::getWireName)
+ .def("getBels", &Arch::getBels)
+ .def("getBelType", &Arch::getBelType)
+ .def("getWireBelPin", &Arch::getWireBelPin)
+ .def("getBelPinUphill", &Arch::getBelPinUphill)
+ .def("getBelPinsDownhill", &Arch::getBelPinsDownhill)
+ .def("getWires", &Arch::getWires)
+ .def("getPipByName", &Arch::getPipByName)
+ .def("getPipName", &Arch::getPipName)
+ .def("getPips", &Arch::getPips)
+ .def("getPipSrcWire", &Arch::getPipSrcWire)
+ .def("getPipDstWire", &Arch::getPipDstWire)
+ .def("getPipDelay", &Arch::getPipDelay)
+ .def("getPipsDownhill", &Arch::getPipsDownhill)
+ .def("getPipsUphill", &Arch::getPipsUphill)
+ .def("getWireAliases", &Arch::getWireAliases)
+ .def("estimatePosition", &Arch::estimatePosition)
+ .def("estimateDelay", &Arch::estimateDelay);
WRAP_RANGE(Bel);
WRAP_RANGE(BelPin);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 09:25:48 +0000