3 files changed, 34 insertions, 3 deletions
diff --git a/generic/synth/blink.v b/generic/synth/blink.v
new file mode 100644
index 00000000..b7cb1b86
--- /dev/null
+++ b/generic/synth/blink.v
@@ -0,0 +1,9 @@
+module top(input clk, output reg [7:0] leds);
+
+reg [25:0] ctr;
+always @(posedge clk)
+	ctr <= ctr + 1'b1;
+
+assign leds = ctr[25:18];
+
+endmodule
+\ No newline at end of file
diff --git a/generic/synth/cells_map.v b/generic/synth/cells_map.v
index adbccb52..a6027534 100644
--- a/generic/synth/cells_map.v
+++ b/generic/synth/cells_map.v
@@ -7,6 +7,4 @@ module \$lut (A, Y);
 	LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
 endmodule
 
-
-module  \$_DFF_N_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(!C)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
diff --git a/generic/synth/synth_generic.tcl b/generic/synth/synth_generic.tcl
new file mode 100644
index 00000000..c5950788
--- /dev/null
+++ b/generic/synth/synth_generic.tcl
@@ -0,0 +1,24 @@
+# Usage
+# tcl synth_generic.tcl {K} {out.json}
+
+set LUT_K 4
+if {$argc > 0} { set LUT_K [lindex $argv 0] }
+yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
+yosys hierarchy -check
+yosys proc
+yosys flatten
+yosys tribuf -logic
+yosys deminout
+yosys synth -run coarse
+yosys memory_map
+yosys opt -full
+yosys techmap -map +/techmap.v
+yosys opt -fast
+yosys abc -lut $LUT_K
+yosys clean
+yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
+yosys clean
+yosys hierarchy -check
+yosys stat
+
+if {$argc > 1} { yosys write_json [lindex $argv 1] }