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-rw-r--r--ice40/arch.cc44
-rw-r--r--ice40/arch.h13
-rw-r--r--ice40/chipdb.py12
-rw-r--r--ice40/portpins.inc304
4 files changed, 372 insertions, 1 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index f14c8045..be38015a 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -36,6 +36,28 @@ IdString Arch::belTypeToId(BelType type) const
return id("SB_IO");
if (type == TYPE_SB_GB)
return id("SB_GB");
+ if (type == TYPE_ICESTORM_PLL)
+ return id("ICESTORM_PLL");
+ if (type == TYPE_SB_WARMBOOT)
+ return id("SB_WARMBOOT");
+ if (type == TYPE_SB_MAC16)
+ return id("SB_MAC16");
+ if (type == TYPE_ICESTORM_HFOSC)
+ return id("ICESTORM_HFOSC");
+ if (type == TYPE_ICESTORM_LFOSC)
+ return id("ICESTORM_LFOSC");
+ if (type == TYPE_SB_I2C)
+ return id("SB_I2C");
+ if (type == TYPE_SB_SPI)
+ return id("SB_SPI");
+ if (type == TYPE_IO_I3C)
+ return id("IO_I3C");
+ if (type == TYPE_SB_LEDDA_IP)
+ return id("SB_LEDDA_IP");
+ if (type == TYPE_SB_RGBA_DRV)
+ return id("SB_RGBA_DRV");
+ if (type == TYPE_SB_SPRAM256KA)
+ return id("SB_SPRAM256KA");
return IdString();
}
@@ -49,6 +71,28 @@ BelType Arch::belTypeFromId(IdString type) const
return TYPE_SB_IO;
if (type == id("SB_GB"))
return TYPE_SB_GB;
+ if (type == id("ICESTORM_PLL"))
+ return TYPE_ICESTORM_PLL;
+ if (type == id("SB_WARMBOOT"))
+ return TYPE_SB_WARMBOOT;
+ if (type == id("SB_MAC16"))
+ return TYPE_SB_MAC16;
+ if (type == id("ICESTORM_HFOSC"))
+ return TYPE_ICESTORM_HFOSC;
+ if (type == id("ICESTORM_LFOSC"))
+ return TYPE_ICESTORM_LFOSC;
+ if (type == id("SB_I2C"))
+ return TYPE_SB_I2C;
+ if (type == id("SB_SPI"))
+ return TYPE_SB_SPI;
+ if (type == id("IO_I3C"))
+ return TYPE_IO_I3C;
+ if (type == id("SB_LEDDA_IP"))
+ return TYPE_SB_LEDDA_IP;
+ if (type == id("SB_RGBA_DRV"))
+ return TYPE_SB_RGBA_DRV;
+ if (type == id("SB_SPRAM256KA"))
+ return TYPE_SB_SPRAM256KA;
return TYPE_NONE;
}
diff --git a/ice40/arch.h b/ice40/arch.h
index 66292783..74a1efcc 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -51,7 +51,18 @@ enum BelType : int32_t
TYPE_ICESTORM_LC,
TYPE_ICESTORM_RAM,
TYPE_SB_IO,
- TYPE_SB_GB
+ TYPE_SB_GB,
+ TYPE_ICESTORM_PLL,
+ TYPE_SB_WARMBOOT,
+ TYPE_SB_MAC16,
+ TYPE_ICESTORM_HFOSC,
+ TYPE_ICESTORM_LFOSC,
+ TYPE_SB_I2C,
+ TYPE_SB_SPI,
+ TYPE_IO_I3C,
+ TYPE_SB_LEDDA_IP,
+ TYPE_SB_RGBA_DRV,
+ TYPE_SB_SPRAM256KA,
};
enum PortPin : int32_t
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 100aaa6f..92d52288 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -59,6 +59,17 @@ beltypes["ICESTORM_LC"] = 1
beltypes["ICESTORM_RAM"] = 2
beltypes["SB_IO"] = 3
beltypes["SB_GB"] = 4
+beltypes["PLL"] = 5
+beltypes["WARMBOOT"] = 6
+beltypes["MAC16"] = 7
+beltypes["HFOSC"] = 8
+beltypes["LFOSC"] = 9
+beltypes["I2C"] = 10
+beltypes["SPI"] = 11
+beltypes["IO_I3C"] = 12
+beltypes["LEDDA_IP"] = 13
+beltypes["RGBA_DRV"] = 14
+beltypes["SPRAM"] = 15
tiletypes["NONE"] = 0
tiletypes["LOGIC"] = 1
@@ -189,6 +200,7 @@ def pipdelay(src, dst):
assert 0
+
def init_tiletypes(device):
global num_tile_types, tile_sizes, tile_bits
if device == "5k":
diff --git a/ice40/portpins.inc b/ice40/portpins.inc
index c06681a7..d78625d1 100644
--- a/ice40/portpins.inc
+++ b/ice40/portpins.inc
@@ -106,3 +106,307 @@ X(D_IN_1)
X(USER_SIGNAL_TO_GLOBAL_BUFFER)
X(GLOBAL_BUFFER_OUTPUT)
+
+X(REFERENCECLK)
+X(EXTFEEDBACK)
+X(DYNAMICDELAY_0)
+X(DYNAMICDELAY_1)
+X(DYNAMICDELAY_2)
+X(DYNAMICDELAY_3)
+X(DYNAMICDELAY_4)
+X(DYNAMICDELAY_5)
+X(DYNAMICDELAY_6)
+X(DYNAMICDELAY_7)
+X(LOCK)
+X(BYPASS)
+X(RESETB)
+X(LATCHINPUTVALUE)
+X(SDO)
+X(SDI)
+X(SCLK)
+
+X(BOOT)
+X(S0)
+X(S1)
+
+X(ADDSUBBOT)
+X(ADDSUBTOP)
+X(AHOLD)
+X(A_0)
+X(A_1)
+X(A_10)
+X(A_11)
+X(A_12)
+X(A_13)
+X(A_14)
+X(A_15)
+X(A_2)
+X(A_3)
+X(A_4)
+X(A_5)
+X(A_6)
+X(A_7)
+X(A_8)
+X(A_9)
+X(BHOLD)
+X(B_0)
+X(B_1)
+X(B_10)
+X(B_11)
+X(B_12)
+X(B_13)
+X(B_14)
+X(B_15)
+X(B_2)
+X(B_3)
+X(B_4)
+X(B_5)
+X(B_6)
+X(B_7)
+X(B_8)
+X(B_9)
+X(CE)
+X(CHOLD)
+X(CI)
+X(CO)
+X(C_0)
+X(C_1)
+X(C_10)
+X(C_11)
+X(C_12)
+X(C_13)
+X(C_14)
+X(C_15)
+X(C_2)
+X(C_3)
+X(C_4)
+X(C_5)
+X(C_6)
+X(C_7)
+X(C_8)
+X(C_9)
+X(DHOLD)
+X(D_0)
+X(D_1)
+X(D_10)
+X(D_11)
+X(D_12)
+X(D_13)
+X(D_14)
+X(D_15)
+X(D_2)
+X(D_3)
+X(D_4)
+X(D_5)
+X(D_6)
+X(D_7)
+X(D_8)
+X(D_9)
+X(IRSTBOT)
+X(IRSTTOP)
+X(OHOLDBOT)
+X(OHOLDTOP)
+X(OLOADBOT)
+X(OLOADTOP)
+X(ORSTBOT)
+X(ORSTTOP)
+X(O_0)
+X(O_1)
+X(O_10)
+X(O_11)
+X(O_12)
+X(O_13)
+X(O_14)
+X(O_15)
+X(O_16)
+X(O_17)
+X(O_18)
+X(O_19)
+X(O_2)
+X(O_20)
+X(O_21)
+X(O_22)
+X(O_23)
+X(O_24)
+X(O_25)
+X(O_26)
+X(O_27)
+X(O_28)
+X(O_29)
+X(O_3)
+X(O_30)
+X(O_31)
+X(O_4)
+X(O_5)
+X(O_6)
+X(O_7)
+X(O_8)
+X(O_9)
+
+X(CLKHF)
+X(CLKHFEN)
+X(CLKHFPU)
+X(CLKHF_FABRIC)
+X(TRIM0)
+X(TRIM1)
+X(TRIM2)
+X(TRIM3)
+X(TRIM4)
+X(TRIM5)
+X(TRIM6)
+X(TRIM7)
+X(TRIM8)
+X(TRIM9)
+
+X(CLKLF)
+X(CLKLFEN)
+X(CLKLFPU)
+X(CLKLF_FABRIC)
+
+X(I2CIRQ)
+X(I2CWKUP)
+X(SBACKO)
+X(SBADRI0)
+X(SBADRI1)
+X(SBADRI2)
+X(SBADRI3)
+X(SBADRI4)
+X(SBADRI5)
+X(SBADRI6)
+X(SBADRI7)
+X(SBCLKI)
+X(SBDATI0)
+X(SBDATI1)
+X(SBDATI2)
+X(SBDATI3)
+X(SBDATI4)
+X(SBDATI5)
+X(SBDATI6)
+X(SBDATI7)
+X(SBDATO0)
+X(SBDATO1)
+X(SBDATO2)
+X(SBDATO3)
+X(SBDATO4)
+X(SBDATO5)
+X(SBDATO6)
+X(SBDATO7)
+X(SBRWI)
+X(SBSTBI)
+X(SCLI)
+X(SCLO)
+X(SCLOE)
+X(SDAI)
+X(SDAO)
+X(SDAOE)
+
+X(MCSNO0)
+X(MCSNO1)
+X(MCSNO2)
+X(MCSNO3)
+X(MCSNOE0)
+X(MCSNOE1)
+X(MCSNOE2)
+X(MCSNOE3)
+X(MI)
+X(MO)
+X(MOE)
+X(SCKI)
+X(SCKO)
+X(SCKOE)
+X(SCSNI)
+X(SI)
+X(SO)
+X(SOE)
+X(SPIIRQ)
+X(SPIWKUP)
+
+X(PU_ENB)
+X(WEAK_PU_ENB)
+
+X(LEDDADDR0)
+X(LEDDADDR1)
+X(LEDDADDR2)
+X(LEDDADDR3)
+X(LEDDCLK)
+X(LEDDCS)
+X(LEDDDAT0)
+X(LEDDDAT1)
+X(LEDDDAT2)
+X(LEDDDAT3)
+X(LEDDDAT4)
+X(LEDDDAT5)
+X(LEDDDAT6)
+X(LEDDDAT7)
+X(LEDDDEN)
+X(LEDDEXE)
+X(LEDDON)
+X(PWMOUT0)
+X(PWMOUT1)
+X(PWMOUT2)
+
+X(CURREN)
+X(RGB0PWM)
+X(RGB1PWM)
+X(RGB2PWM)
+X(RGBLEDEN)
+X(RGB0)
+X(RGB1)
+X(RGB2)
+
+X(ADDRESS_0)
+X(ADDRESS_1)
+X(ADDRESS_10)
+X(ADDRESS_11)
+X(ADDRESS_12)
+X(ADDRESS_13)
+X(ADDRESS_2)
+X(ADDRESS_3)
+X(ADDRESS_4)
+X(ADDRESS_5)
+X(ADDRESS_6)
+X(ADDRESS_7)
+X(ADDRESS_8)
+X(ADDRESS_9)
+X(CHIPSELECT)
+X(CLOCK)
+X(DATAIN_0)
+X(DATAIN_1)
+X(DATAIN_10)
+X(DATAIN_11)
+X(DATAIN_12)
+X(DATAIN_13)
+X(DATAIN_14)
+X(DATAIN_15)
+X(DATAIN_2)
+X(DATAIN_3)
+X(DATAIN_4)
+X(DATAIN_5)
+X(DATAIN_6)
+X(DATAIN_7)
+X(DATAIN_8)
+X(DATAIN_9)
+X(DATAOUT_0)
+X(DATAOUT_1)
+X(DATAOUT_10)
+X(DATAOUT_11)
+X(DATAOUT_12)
+X(DATAOUT_13)
+X(DATAOUT_14)
+X(DATAOUT_15)
+X(DATAOUT_2)
+X(DATAOUT_3)
+X(DATAOUT_4)
+X(DATAOUT_5)
+X(DATAOUT_6)
+X(DATAOUT_7)
+X(DATAOUT_8)
+X(DATAOUT_9)
+X(MASKWREN_0)
+X(MASKWREN_1)
+X(MASKWREN_2)
+X(MASKWREN_3)
+X(POWEROFF)
+X(SLEEP)
+X(STANDBY)
+X(WREN)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 19:16:54 +0000