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-rw-r--r--common/nextpnr.cc4
-rw-r--r--common/place_common.cc4
-rw-r--r--ecp5/arch.cc2
-rw-r--r--ecp5/arch.h2
-rw-r--r--generic/arch.cc2
-rw-r--r--generic/arch.h2
-rw-r--r--ice40/arch.cc2
-rw-r--r--ice40/arch.h2
-rw-r--r--ice40/arch_place.cc2
-rw-r--r--ice40/arch_pybindings.cc4
-rw-r--r--ice40/bitstream.cc6
-rw-r--r--ice40/main.cc20
12 files changed, 26 insertions, 26 deletions
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index ac292e77..74747642 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -67,7 +67,7 @@ WireId Context::getNetinfoSourceWire(NetInfo *net_info) const
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
- return getWireBelPin(src_bel, portPinFromId(driver_port));
+ return getBelPinWire(src_bel, portPinFromId(driver_port));
}
WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
@@ -85,7 +85,7 @@ WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
if (user_port_it != user_info.cell->pins.end())
user_port = user_port_it->second;
- return getWireBelPin(dst_bel, portPinFromId(user_port));
+ return getBelPinWire(dst_bel, portPinFromId(user_port));
}
delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const
diff --git a/common/place_common.cc b/common/place_common.cc
index 370eff23..95b7b2aa 100644
--- a/common/place_common.cc
+++ b/common/place_common.cc
@@ -36,7 +36,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (driver_cell->bel == BelId())
return 0;
ctx->estimatePosition(driver_cell->bel, driver_x, driver_y, driver_gb);
- WireId drv_wire = ctx->getWireBelPin(driver_cell->bel, ctx->portPinFromId(net->driver.port));
+ WireId drv_wire = ctx->getBelPinWire(driver_cell->bel, ctx->portPinFromId(net->driver.port));
if (driver_gb)
return 0;
float worst_slack = 1000;
@@ -48,7 +48,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (load_cell->bel == BelId())
continue;
if (ctx->timing_driven && type == MetricType::COST) {
- WireId user_wire = ctx->getWireBelPin(load_cell->bel, ctx->portPinFromId(load.port));
+ WireId user_wire = ctx->getBelPinWire(load_cell->bel, ctx->portPinFromId(load.port));
delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
float slack = ctx->getDelayNS(load.budget) - ctx->getDelayNS(raw_wl);
if (slack < 0)
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 1510a27f..f6ee0711 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -206,7 +206,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
return br;
}
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
{
WireId ret;
diff --git a/ecp5/arch.h b/ecp5/arch.h
index bf36ef2f..234773e3 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -484,7 +484,7 @@ struct Arch : BaseCtx
return locInfo(bel)->bel_data[bel.index].type;
}
- WireId getWireBelPin(BelId bel, PortPin pin) const;
+ WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const
{
diff --git a/generic/arch.cc b/generic/arch.cc
index 447aaa35..1a8b1a67 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -215,7 +215,7 @@ const std::vector<BelId> &Arch::getBelsByType(BelType type) const
BelType Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
BelPin Arch::getBelPinUphill(WireId wire) const { return wires.at(wire).uphill_bel_pin; }
diff --git a/generic/arch.h b/generic/arch.h
index f4ca4383..7bcb965f 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -145,7 +145,7 @@ struct Arch : BaseCtx
const std::vector<BelId> &getBels() const;
const std::vector<BelId> &getBelsByType(BelType type) const;
BelType getBelType(BelId bel) const;
- WireId getWireBelPin(BelId bel, PortPin pin) const;
+ WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const;
const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const;
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 3833dcb7..a670f286 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -308,7 +308,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
return br;
}
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
{
WireId ret;
diff --git a/ice40/arch.h b/ice40/arch.h
index 9a8ec7bc..566f807a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -465,7 +465,7 @@ struct Arch : BaseCtx
return chip_info->bel_data[bel.index].type;
}
- WireId getWireBelPin(BelId bel, PortPin pin) const;
+ WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const
{
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 116ab7d3..cf1276a7 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -110,7 +110,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
} else if (cell->type == id_sb_gb) {
NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
const NetInfo *net = cell->ports.at(id_glb_buf_out).net;
- IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
+ IdString glb_net = getWireName(getBelPinWire(bel, PIN_GLOBAL_BUFFER_OUTPUT));
int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
if (net->is_reset && net->is_enable)
return false;
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index fd5109b4..a1ce9f5b 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -82,8 +82,8 @@ void arch_wrap_python()
fn_wrapper_1a<Context, decltype(&Context::getBelsAtSameTile), &Context::getBelsAtSameTile, wrap_context<BelRange>,
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelsAtSameTile");
- fn_wrapper_2a<Context, decltype(&Context::getWireBelPin), &Context::getWireBelPin, conv_to_str<WireId>,
- conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getWireBelPin");
+ fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
+ conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
fn_wrapper_1a<Context, decltype(&Context::getBelPinUphill), &Context::getBelPinUphill, wrap_context<BelPin>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinUphill");
fn_wrapper_1a<Context, decltype(&Context::getBelPinsDownhill), &Context::getBelPinsDownhill,
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 7fd3f8ac..9f5d1f66 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -319,8 +319,8 @@ void write_asc(const Context *ctx, std::ostream &out)
NPNR_ASSERT(iez != -1);
bool input_en = false;
- if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||
- (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {
+ if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) ||
+ (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) {
input_en = true;
}
@@ -762,7 +762,7 @@ bool read_asc(Context *ctx, std::istream &in)
if (cell.second->bel != BelId()) {
for (auto &port : cell.second->ports) {
PortPin pin = ctx->portPinFromId(port.first);
- WireId wire = ctx->getWireBelPin(cell.second->bel, pin);
+ WireId wire = ctx->getBelPinWire(cell.second->bel, pin);
if (wire != WireId()) {
IdString name = ctx->getBoundWireNet(wire);
if (name != IdString()) {
diff --git a/ice40/main.cc b/ice40/main.cc
index b84d6d92..24b49184 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -322,25 +322,25 @@ int main(int argc, char *argv[])
src_wires.push_back(w);*/
for (auto b : ctx->getBels()) {
if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
- src_wires.push_back(ctx->getWireBelPin(b, PIN_O));
+ src_wires.push_back(ctx->getBelPinWire(b, PIN_O));
}
if (ctx->getBelType(b) == TYPE_SB_IO) {
- src_wires.push_back(ctx->getWireBelPin(b, PIN_D_IN_0));
+ src_wires.push_back(ctx->getBelPinWire(b, PIN_D_IN_0));
}
}
for (auto b : ctx->getBels()) {
if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_I0));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_I1));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_I2));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_I3));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_CEN));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_CIN));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_I0));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_I1));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_I2));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_I3));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_CEN));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_CIN));
}
if (ctx->getBelType(b) == TYPE_SB_IO) {
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_D_OUT_0));
- dst_wires.push_back(ctx->getWireBelPin(b, PIN_OUTPUT_ENABLE));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_D_OUT_0));
+ dst_wires.push_back(ctx->getBelPinWire(b, PIN_OUTPUT_ENABLE));
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-21 04:40:45 +0000