diff options
| -rw-r--r-- | common/place_sa.cc | 9 | ||||
| -rw-r--r-- | common/timing.cc | 7 | ||||
| -rw-r--r-- | ice40/arch.cc | 2 | ||||
| -rw-r--r-- | ice40/main.cc | 12 |
4 files changed, 23 insertions, 7 deletions
diff --git a/common/place_sa.cc b/common/place_sa.cc index 0a60adc8..485ddc88 100644 --- a/common/place_sa.cc +++ b/common/place_sa.cc @@ -314,7 +314,9 @@ class SAPlacer load_cell->bel, ctx->portPinFromId(load.port)); // wirelength += std::abs(load_x - driver_x) + std::abs(load_y - // driver_y); - wirelength += ctx->estimateDelay(drv_wire, user_wire); + delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire); + wirelength += 100 * (ctx->getDelayNS(raw_wl) / ctx->getDelayNS(load.budget)); + // wirelength += pow(ctx->estimateDelay(drv_wire, user_wire), 2.0); } return wirelength; } @@ -376,9 +378,8 @@ class SAPlacer delta = new_wirelength - curr_wirelength; n_move++; // SA acceptance criterea - if (delta < 0 || - (temp > 1e-6 && - (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) { + if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <= + std::exp(-delta / temp))) { n_accept++; if (delta < 0) improved = true; diff --git a/common/timing.cc b/common/timing.cc index a4bda3bb..8da26077 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -101,6 +101,8 @@ void assign_budget(Context *ctx, float default_clock) } } } + const bool debug = true; + // Post-allocation check for (auto net : ctx->nets) { for (auto user : net.second->users) { @@ -109,6 +111,11 @@ void assign_budget(Context *ctx, float default_clock) "timing budget of %fns\n", user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx), ctx->getDelayNS(user.budget)); + if (debug) + log_warning("port %s.%s, connected to net '%s', has " + "timing budget of %fns\n", + user.cell->name.c_str(ctx), user.port.c_str(ctx), + net.first.c_str(ctx), ctx->getDelayNS(user.budget)); } } } diff --git a/ice40/arch.cc b/ice40/arch.cc index fd93a91d..d7673dd0 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -313,7 +313,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const delay_t x2 = chip_info->wire_data[dst.index].x; delay_t y2 = chip_info->wire_data[dst.index].y; - return fabsf(x1 - x2) + fabsf(y1 - y2); + return delay_t(50 * (fabsf(x1 - x2) + fabsf(y1 - y2))); } // ----------------------------------------------------------------------- diff --git a/ice40/main.cc b/ice40/main.cc index 13d8ac0b..d83018ef 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -224,8 +224,16 @@ int main(int argc, char *argv[]) if (vm.count("tmfuzz")) { std::vector<WireId> src_wires, dst_wires; - for (auto w : ctx.getWires()) - src_wires.push_back(w); + /*for (auto w : ctx.getWires()) + src_wires.push_back(w);*/ + for (auto b : ctx.getBels()) { + if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { + src_wires.push_back(ctx.getWireBelPin(b, PIN_O)); + } + if (ctx.getBelType(b) == TYPE_SB_IO) { + src_wires.push_back(ctx.getWireBelPin(b, PIN_D_IN_0)); + } + } for (auto b : ctx.getBels()) { if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { |