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-rw-r--r--CMakeLists.txt2
-rw-r--r--common/design.h4
-rw-r--r--common/design_utils.cc4
-rw-r--r--common/design_utils.h5
-rw-r--r--common/handle_error.cc5
-rw-r--r--common/log.cc4
-rw-r--r--common/log.h4
-rw-r--r--common/nextpnr.h40
-rw-r--r--common/place.cc4
-rw-r--r--common/place.h4
-rw-r--r--common/pybindings.cc5
-rw-r--r--common/pybindings.h9
-rw-r--r--common/pycontainers.h5
-rw-r--r--common/route.cc23
-rw-r--r--common/route.h4
-rw-r--r--common/rulecheck.cc4
-rw-r--r--dummy/chip.cc4
-rw-r--r--dummy/chip.h4
-rw-r--r--dummy/main.cc2
-rw-r--r--dummy/pybindings.cc4
-rw-r--r--frontend/json/jsonparse.cc4
-rw-r--r--frontend/json/jsonparse.h4
-rw-r--r--gui/fpgaviewwidget.h4
-rw-r--r--gui/mainwindow.h3
-rw-r--r--ice40/bitstream.cc4
-rw-r--r--ice40/bitstream.h4
-rw-r--r--ice40/cells.cc4
-rw-r--r--ice40/cells.h4
-rw-r--r--ice40/chip.cc4
-rw-r--r--ice40/chip.h20
-rw-r--r--ice40/chipdb.py9
-rw-r--r--ice40/family.cmake1
-rw-r--r--ice40/pybindings.cc4
33 files changed, 167 insertions, 42 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 19558081..b0976d9a 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -96,7 +96,7 @@ foreach (family ${FAMILIES})
foreach (target ${family_targets})
# Include family-specific source files to all family targets and set defines appropriately
target_include_directories(${target} PRIVATE ${family}/)
- target_compile_definitions(${target} PRIVATE ARCH_${ufamily} ARCHNAME=${family} -DQT_NO_KEYWORDS)
+ target_compile_definitions(${target} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family} ARCH_${ufamily} ARCHNAME=${family} -DQT_NO_KEYWORDS)
target_link_libraries(${target} LINK_PUBLIC ${Boost_LIBRARIES} ${PYTHON_LIBRARIES} ${GUI_LIBRARY_FILES})
endforeach (target)
diff --git a/common/design.h b/common/design.h
index ae2657f2..e763ed48 100644
--- a/common/design.h
+++ b/common/design.h
@@ -24,6 +24,8 @@
#error Include "design.h" via "nextpnr.h" only.
#endif
+NEXTPNR_NAMESPACE_BEGIN
+
struct CellInfo;
struct PortRef
@@ -81,4 +83,6 @@ struct Design
std::unordered_map<IdString, CellInfo *> cells;
};
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/common/design_utils.cc b/common/design_utils.cc
index 8b52697b..85895a75 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -19,6 +19,8 @@
#include "design_utils.h"
+NEXTPNR_NAMESPACE_BEGIN
+
void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
IdString rep_name)
{
@@ -46,3 +48,5 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
assert(false);
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/design_utils.h b/common/design_utils.h
index 43ff180b..b57c1cb6 100644
--- a/common/design_utils.h
+++ b/common/design_utils.h
@@ -21,6 +21,9 @@
#ifndef DESIGN_UTILS_H
#define DESIGN_UTILS_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
/*
Utilities for design manipulation, intended for use inside packing algorithms
*/
@@ -61,4 +64,6 @@ CellInfo *net_driven_by(NetInfo *net, F1 cell_pred, IdString port)
}
}
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/common/handle_error.cc b/common/handle_error.cc
index 55ec75fb..7076c188 100644
--- a/common/handle_error.cc
+++ b/common/handle_error.cc
@@ -1,8 +1,11 @@
#include <Python.h>
#include <boost/python.hpp>
+#include "nextpnr.h"
namespace py = boost::python;
+NEXTPNR_NAMESPACE_BEGIN
+
// Parses the value of the active python exception
// NOTE SHOULD NOT BE CALLED IF NO EXCEPTION
std::string parse_python_exception()
@@ -56,3 +59,5 @@ std::string parse_python_exception()
}
return ret;
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/log.cc b/common/log.cc
index e72633bc..cbd3c171 100644
--- a/common/log.cc
+++ b/common/log.cc
@@ -28,6 +28,8 @@
#include "log.h"
+NEXTPNR_NAMESPACE_BEGIN
+
std::vector<FILE *> log_files;
std::vector<std::ostream *> log_streams;
FILE *log_errfile = NULL;
@@ -233,3 +235,5 @@ void log_flush()
void log_cell(CellInfo *cell, std::string indent) {}
void log_net(NetInfo *net, std::string indent) {}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/log.h b/common/log.h
index 085f72ee..afe7a047 100644
--- a/common/log.h
+++ b/common/log.h
@@ -34,6 +34,8 @@
#define NXP_NORETURN
#define NXP_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
+NEXTPNR_NAMESPACE_BEGIN
+
struct log_cmd_error_exception
{
};
@@ -99,4 +101,6 @@ static inline void log_assert_worker(bool cond, const char *expr,
#define log_ping() \
log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 453af496..0c74c1ad 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -27,42 +27,40 @@
#ifndef NEXTPNR_H
#define NEXTPNR_H
+#ifdef NEXTPNR_NAMESPACE
+#define NEXTPNR_NAMESPACE_PREFIX NEXTPNR_NAMESPACE::
+#define NEXTPNR_NAMESPACE_BEGIN namespace NEXTPNR_NAMESPACE {
+#define NEXTPNR_NAMESPACE_END }
+#define USING_NEXTPNR_NAMESPACE using namespace NEXTPNR_NAMESPACE;
+#else
+#define NEXTPNR_NAMESPACE_PREFIX
+#define NEXTPNR_NAMESPACE_BEGIN
+#define NEXTPNR_NAMESPACE_END
+#define USING_NEXTPNR_NAMESPACE
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
// replace with proper IdString later
typedef std::string IdString;
struct GraphicElement
{
- // This will control colour, and there should be separate
- // visibility controls in some cases also
- enum
- {
- // Wires entirely inside tiles, e.g. between switchbox and bels
- G_LOCAL_WIRES,
- // Standard inter-tile routing
- G_GENERAL_WIRES,
- // Special inter-tile wires, e.g. carry chains
- G_DEDICATED_WIRES,
- G_BEL_OUTLINE,
- G_SWITCHBOX_OUTLINE,
- G_TILE_OUTLINE,
- G_BEL_PINS,
- G_SWITCHBOX_PINS,
- G_BEL_MISC,
- G_TILE_MISC,
- } style;
-
enum
{
+ G_NONE,
G_LINE,
G_BOX,
G_CIRCLE,
G_LABEL
- } type;
+ } type = G_NONE;
- float x1, y1, x2, y2, z;
+ float x1 = 0, y1 = 0, x2 = 0, y2 = 0, z = 0;
std::string text;
};
+NEXTPNR_NAMESPACE_END
+
#include "chip.h"
#include "design.h"
diff --git a/common/place.cc b/common/place.cc
index 0223c78f..eba71a50 100644
--- a/common/place.cc
+++ b/common/place.cc
@@ -31,6 +31,8 @@
#include "log.h"
#include "place.h"
+NEXTPNR_NAMESPACE_BEGIN
+
void place_design(Design *design)
{
std::set<IdString> types_used;
@@ -115,3 +117,5 @@ void place_design(Design *design)
}
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/place.h b/common/place.h
index a8b86595..7df84873 100644
--- a/common/place.h
+++ b/common/place.h
@@ -21,6 +21,10 @@
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
extern void place_design(Design *design);
+NEXTPNR_NAMESPACE_END
+
#endif // PLACE_H
diff --git a/common/pybindings.cc b/common/pybindings.cc
index d941436b..8aa831ca 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -25,6 +25,8 @@
#include <fstream>
+NEXTPNR_NAMESPACE_BEGIN
+
// Required to determine concatenated module name (which differs for different
// archs)
#define PASTER(x, y) x##_##y
@@ -64,7 +66,6 @@ Design load_design_shim(std::string filename, ChipArgs args)
BOOST_PYTHON_MODULE(MODULE_NAME)
{
class_<GraphicElement>("GraphicElement")
- .def_readwrite("style", &GraphicElement::style)
.def_readwrite("type", &GraphicElement::type)
.def_readwrite("x1", &GraphicElement::x1)
.def_readwrite("y1", &GraphicElement::y1)
@@ -178,3 +179,5 @@ void execute_python_file(const char *python_file)
std::cout << "Error in Python: " << perror_str << std::endl;
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/pybindings.h b/common/pybindings.h
index bb060718..de6aa4c7 100644
--- a/common/pybindings.h
+++ b/common/pybindings.h
@@ -29,6 +29,11 @@
#include <boost/python/suite/indexing/vector_indexing_suite.hpp>
#include <stdexcept>
#include <utility>
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
using namespace boost::python;
/*
@@ -110,8 +115,8 @@ void deinit_python();
void execute_python_file(const char *python_file);
-std::string parse_python_exception();
-
void arch_appendinittab();
+NEXTPNR_NAMESPACE_END
+
#endif /* end of include guard: COMMON_PYBINDINGS_HH */
diff --git a/common/pycontainers.h b/common/pycontainers.h
index 423e36f5..992d0de9 100644
--- a/common/pycontainers.h
+++ b/common/pycontainers.h
@@ -27,6 +27,9 @@
#include <stdexcept>
#include <type_traits>
#include <utility>
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
using namespace boost::python;
@@ -270,4 +273,6 @@ template <typename T> struct map_wrapper
map_wrapper<t>().wrap(#name, #name "KeyValue", #name "KeyValueIter", \
#name "Iterator")
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/common/route.cc b/common/route.cc
index b98db259..ca76024f 100644
--- a/common/route.cc
+++ b/common/route.cc
@@ -22,22 +22,23 @@
#include "log.h"
#include "route.h"
+NEXTPNR_NAMESPACE_BEGIN
+
struct QueuedWire
{
WireId wire;
PipId pip;
DelayInfo delay;
-};
-namespace std {
-template <> struct greater<QueuedWire>
-{
- bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const noexcept
+ struct Greater
{
- return lhs.delay.avgDelay() > rhs.delay.avgDelay();
- }
+ bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const
+ noexcept
+ {
+ return lhs.delay.avgDelay() > rhs.delay.avgDelay();
+ }
+ };
};
-} // namespace std
void route_design(Design *design)
{
@@ -99,7 +100,7 @@ void route_design(Design *design)
std::unordered_map<WireId, QueuedWire> visited;
std::priority_queue<QueuedWire, std::vector<QueuedWire>,
- std::greater<QueuedWire>>
+ QueuedWire::Greater>
queue;
for (auto &it : src_wires) {
@@ -135,7 +136,7 @@ void route_design(Design *design)
if (next_qw.wire == dst_wire) {
std::priority_queue<QueuedWire, std::vector<QueuedWire>,
- std::greater<QueuedWire>>
+ QueuedWire::Greater>
empty_queue;
std::swap(queue, empty_queue);
break;
@@ -169,3 +170,5 @@ void route_design(Design *design)
}
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/common/route.h b/common/route.h
index 5ecbd823..d9c240b3 100644
--- a/common/route.h
+++ b/common/route.h
@@ -22,6 +22,10 @@
#include "design.h"
+NEXTPNR_NAMESPACE_BEGIN
+
extern void route_design(Design *design);
+NEXTPNR_NAMESPACE_END
+
#endif // ROUTE_H
diff --git a/common/rulecheck.cc b/common/rulecheck.cc
index 4fc3f73a..c0139a85 100644
--- a/common/rulecheck.cc
+++ b/common/rulecheck.cc
@@ -3,6 +3,8 @@
#include "log.h"
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
bool check_all_nets_driven(Design *design)
{
const bool debug = false;
@@ -70,3 +72,5 @@ bool check_all_nets_driven(Design *design)
log_info(" Verified!\n");
return true;
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/dummy/chip.cc b/dummy/chip.cc
index 0e23a20a..23aa0e9d 100644
--- a/dummy/chip.cc
+++ b/dummy/chip.cc
@@ -19,6 +19,8 @@
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
Chip::Chip(ChipArgs) {}
std::string Chip::getChipName() { return "Dummy"; }
@@ -156,3 +158,5 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
static std::vector<GraphicElement> ret;
return ret;
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/dummy/chip.h b/dummy/chip.h
index 274f0e8e..e5a6dd56 100644
--- a/dummy/chip.h
+++ b/dummy/chip.h
@@ -24,6 +24,8 @@
#error Include "chip.h" via "nextpnr.h" only.
#endif
+NEXTPNR_NAMESPACE_BEGIN
+
struct DelayInfo
{
float delay = 0;
@@ -116,4 +118,6 @@ struct Chip
std::vector<GraphicElement> getFrameGraphics() const;
};
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/dummy/main.cc b/dummy/main.cc
index df5333ca..3b9e6ba3 100644
--- a/dummy/main.cc
+++ b/dummy/main.cc
@@ -23,6 +23,8 @@
#include "mainwindow.h"
#include "nextpnr.h"
+USING_NEXTPNR_NAMESPACE
+
int main(int argc, char *argv[])
{
Design design(ChipArgs{});
diff --git a/dummy/pybindings.cc b/dummy/pybindings.cc
index a0b6322e..ec0e20b2 100644
--- a/dummy/pybindings.cc
+++ b/dummy/pybindings.cc
@@ -21,4 +21,8 @@
#include "pybindings.h"
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
void arch_wrap_python() { class_<ChipArgs>("ChipArgs"); }
+
+NEXTPNR_NAMESPACE_END
diff --git a/frontend/json/jsonparse.cc b/frontend/json/jsonparse.cc
index 8a46c909..5f394217 100644
--- a/frontend/json/jsonparse.cc
+++ b/frontend/json/jsonparse.cc
@@ -29,6 +29,8 @@
#include <string>
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
extern bool check_all_nets_driven(Design *design);
namespace JsonParser {
@@ -700,3 +702,5 @@ void parse_json_file(std::istream *&f, std::string &filename, Design *design)
auto *parser = new JsonParser::JsonFrontend();
parser->execute(f, filename, design);
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/frontend/json/jsonparse.h b/frontend/json/jsonparse.h
index 8d863029..ca0844e7 100644
--- a/frontend/json/jsonparse.h
+++ b/frontend/json/jsonparse.h
@@ -24,6 +24,10 @@
#include <string>
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
extern void parse_json_file(std::istream *&, std::string &, Design *);
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/gui/fpgaviewwidget.h b/gui/fpgaviewwidget.h
index 4e6838e1..1d05afb7 100644
--- a/gui/fpgaviewwidget.h
+++ b/gui/fpgaviewwidget.h
@@ -7,6 +7,9 @@
#include <QPainter>
#include "nextpnr.h"
+// FIXME
+USING_NEXTPNR_NAMESPACE
+
class FPGAViewWidget : public QOpenGLWidget, protected QOpenGLFunctions
{
Q_OBJECT
@@ -45,4 +48,5 @@ class FPGAViewWidget : public QOpenGLWidget, protected QOpenGLFunctions
QPoint m_lastPos;
Design *design;
};
+
#endif
diff --git a/gui/mainwindow.h b/gui/mainwindow.h
index c782a4a6..6f3e515f 100644
--- a/gui/mainwindow.h
+++ b/gui/mainwindow.h
@@ -6,6 +6,9 @@
#include <QMainWindow>
+// FIXME
+USING_NEXTPNR_NAMESPACE
+
namespace Ui {
class MainWindow;
}
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 944e80c2..7952a8a1 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -20,6 +20,8 @@
#include "bitstream.h"
#include <vector>
+NEXTPNR_NAMESPACE_BEGIN
+
inline TileType tile_at(const Chip &chip, int x, int y)
{
return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
@@ -311,3 +313,5 @@ void write_asc(const Design &design, std::ostream &out)
}
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ice40/bitstream.h b/ice40/bitstream.h
index fecc14e1..11547163 100644
--- a/ice40/bitstream.h
+++ b/ice40/bitstream.h
@@ -23,6 +23,10 @@
#include <iostream>
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
void write_asc(const Design &design, std::ostream &out);
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 328b5f2d..1e9a012b 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -21,6 +21,8 @@
#include "design_utils.h"
#include "log.h"
+NEXTPNR_NAMESPACE_BEGIN
+
static void add_port(CellInfo *cell, IdString name, PortType dir)
{
cell->ports[name] = PortInfo{name, nullptr, dir};
@@ -108,3 +110,5 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
replace_port(dff, "D", lc, "I0");
}
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ice40/cells.h b/ice40/cells.h
index 1fa85413..1c2e0d0f 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -22,6 +22,8 @@
#ifndef ICE40_CELLS_H
#define ICE40_CELLS_H
+NEXTPNR_NAMESPACE_BEGIN
+
// Create a standard iCE40 cell and return it
// Name will be automatically assigned if not specified
CellInfo *create_ice_cell(Design *design, IdString type,
@@ -51,4 +53,6 @@ inline bool is_ff(const CellInfo *cell)
// ignored
void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/ice40/chip.cc b/ice40/chip.cc
index 42252fa0..29da5644 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -20,6 +20,8 @@
#include "log.h"
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
// -----------------------------------------------------------------------
IdString belTypeToId(BelType type)
@@ -327,3 +329,5 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
return ret;
}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ice40/chip.h b/ice40/chip.h
index 451be9ce..9dc0498c 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -24,6 +24,8 @@
#error Include "chip.h" via "nextpnr.h" only.
#endif
+NEXTPNR_NAMESPACE_BEGIN
+
struct DelayInfo
{
float delay = 0;
@@ -210,32 +212,36 @@ struct BelPin
PortPin pin;
};
+NEXTPNR_NAMESPACE_END
+
namespace std {
-template <> struct hash<BelId>
+template <> struct hash<NEXTPNR_NAMESPACE::BelId>
{
- std::size_t operator()(const BelId &bel) const noexcept
+ std::size_t operator()(const NEXTPNR_NAMESPACE::BelId &bel) const noexcept
{
return bel.index;
}
};
-template <> struct hash<WireId>
+template <> struct hash<NEXTPNR_NAMESPACE::WireId>
{
- std::size_t operator()(const WireId &wire) const noexcept
+ std::size_t operator()(const NEXTPNR_NAMESPACE::WireId &wire) const noexcept
{
return wire.index;
}
};
-template <> struct hash<PipId>
+template <> struct hash<NEXTPNR_NAMESPACE::PipId>
{
- std::size_t operator()(const PipId &wire) const noexcept
+ std::size_t operator()(const NEXTPNR_NAMESPACE::PipId &wire) const noexcept
{
return wire.index;
}
};
} // namespace std
+NEXTPNR_NAMESPACE_BEGIN
+
// -----------------------------------------------------------------------
struct BelIterator
@@ -677,4 +683,6 @@ struct Chip
std::vector<GraphicElement> getFrameGraphics() const;
};
+NEXTPNR_NAMESPACE_END
+
#endif
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 34366679..9b246f8b 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -312,6 +312,8 @@ elif dev_name == "5k":
add_bel_gb(19, 0, 7)
print('#include "nextpnr.h"')
+print('namespace {')
+print('USING_NEXTPNR_NAMESPACE')
for bel in range(len(bel_name)):
print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel])))
@@ -319,7 +321,7 @@ for bel in range(len(bel_name)):
print(" {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",)))
print("};")
-print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
+print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
for bel in range(len(bel_name)):
print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
@@ -458,8 +460,13 @@ print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid)))
print(",\n".join(tilegrid))
print("};")
+print('}')
+print('NEXTPNR_NAMESPACE_BEGIN')
+
print("ChipInfoPOD chip_info_%s = {" % dev_name)
print(" %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo)))
print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name))
print("};")
+
+print('NEXTPNR_NAMESPACE_END')
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 33c5c20e..1ed2ecf3 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -11,6 +11,7 @@ set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py)
file(MAKE_DIRECTORY ice40/chipdbs/)
add_library(ice40_chipdb OBJECT ice40/chipdbs/)
target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
+target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
target_include_directories(ice40_chipdb PRIVATE ${family}/)
foreach (dev ${devices})
set(DEV_TXT_DB /usr/local/share/icebox/chipdb-${dev}.txt)
diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc
index c00bf6b9..9094fe7c 100644
--- a/ice40/pybindings.cc
+++ b/ice40/pybindings.cc
@@ -21,6 +21,8 @@
#include "pybindings.h"
#include "nextpnr.h"
+NEXTPNR_NAMESPACE_BEGIN
+
void arch_wrap_python()
{
class_<ChipArgs>("ChipArgs").def_readwrite("type", &ChipArgs::type);
@@ -80,3 +82,5 @@ void arch_wrap_python()
WRAP_RANGE(AllPip);
WRAP_RANGE(Pip);
}
+
+NEXTPNR_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 01:10:48 +0000