diff options
-rw-r--r-- | ice40/cells.cc | 4 | ||||
-rw-r--r-- | ice40/chipdb.py | 22 | ||||
-rw-r--r-- | ice40/constids.inc | 2 |
3 files changed, 22 insertions, 6 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc index 3906334f..53f2e10c 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -244,8 +244,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri add_port(ctx, new_cell.get(), "LOCK", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT); add_port(ctx, new_cell.get(), "PLLOUT_B", PORT_OUT); - add_port(ctx, new_cell.get(), "PLLOUTGLOBALA", PORT_OUT); - add_port(ctx, new_cell.get(), "PLLOUTGLOBALB", PORT_OUT); + add_port(ctx, new_cell.get(), "PLLOUT_A_GLOBAL", PORT_OUT); + add_port(ctx, new_cell.get(), "PLLOUT_B_GLOBAL", PORT_OUT); } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 6db6c26b..96231b26 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -863,6 +863,10 @@ def add_bel_io(x, y, z): add_bel_input(bel, wire_dout_1, "D_OUT_1") add_bel_input(bel, wire_out_en, "OUTPUT_ENABLE") + for gidx, ginfo in glbinfo.items(): + if (ginfo['pi_gb_x'], ginfo['pi_gb_y'], ginfo['pi_gb_pio']) == (x,y,z): + add_bel_output(bel, wire_names[(x, y, "glb_netwk_%d" % gidx)], "GLOBAL_BUFFER_OUTPUT") + def add_bel_ram(x, y): bel = len(bel_name) bel_name.append("X%d/Y%d/ram" % (x, y)) @@ -920,6 +924,18 @@ def is_ec_output(ec_entry): def is_ec_pll_clock_output(ec, ec_entry): return ec[0] == 'PLL' and ec_entry[0] in ('PLLOUT_A', 'PLLOUT_B') +def add_pll_clock_output(bel, ec, entry): + # Fabric output + io_x, io_y, io_z = entry[1] + io_zs = 'io_{}/D_IN_0'.format(io_z) + io_z = int(io_z) + add_bel_output(bel, wire_names[(io_x, io_y, io_zs)], entry[0]) + + # Global output + for gidx, ginfo in glbinfo.items(): + if (ginfo['pi_gb_x'], ginfo['pi_gb_y'], ginfo['pi_gb_pio']) == (io_x, io_y, io_z): + add_bel_output(bel, wire_names[(io_x, io_y, "glb_netwk_%d" % gidx)], entry[0] + '_GLOBAL') + def add_bel_ec(ec): ectype, x, y, z = ec bel = len(bel_name) @@ -929,15 +945,13 @@ def add_bel_ec(ec): bel_pos.append((x, y, z)) bel_wires.append(list()) for entry in extra_cells[ec]: - if is_ec_wire(entry) and "glb_netwk_" not in entry[1][2]: # TODO: osc glb output conflicts with GB + if is_ec_wire(entry): if is_ec_output(entry): add_bel_output(bel, wire_names[entry[1]], entry[0]) else: add_bel_input(bel, wire_names[entry[1]], entry[0]) elif is_ec_pll_clock_output(ec, entry): - x, y, z = entry[1] - z = 'io_{}/D_IN_0'.format(z) - add_bel_output(bel, wire_names[(x, y, z)], entry[0]) + add_pll_clock_output(bel, ec, entry) else: extra_cell_config[bel].append(entry) diff --git a/ice40/constids.inc b/ice40/constids.inc index dad08e59..e1c4992e 100644 --- a/ice40/constids.inc +++ b/ice40/constids.inc @@ -121,6 +121,8 @@ X(DYNAMICDELAY_7) X(LOCK) X(PLLOUT_A) X(PLLOUT_B) +X(PLLOUT_A_GLOBAL) +X(PLLOUT_B_GLOBAL) X(BYPASS) X(RESETB) X(LATCHINPUTVALUE) |