diff options
| -rw-r--r-- | generic/examples/.gitignore | 3 | ||||
| -rw-r--r-- | generic/examples/blinky.v | 13 | ||||
| -rw-r--r-- | generic/examples/blinky_tb.v | 38 | ||||
| -rwxr-xr-x | generic/examples/simtest.sh | 7 | ||||
| -rw-r--r-- | generic/synth/prims.v | 13 |
5 files changed, 67 insertions, 7 deletions
diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore index 38e95de5..ad2fba28 100644 --- a/generic/examples/.gitignore +++ b/generic/examples/.gitignore @@ -1,3 +1,6 @@ blinky.fasm __pycache__ *.pyc +pnrblinky.v +/blinky_simtest +*.vcd diff --git a/generic/examples/blinky.v b/generic/examples/blinky.v index b7cb1b86..42becb72 100644 --- a/generic/examples/blinky.v +++ b/generic/examples/blinky.v @@ -1,9 +1,12 @@ -module top(input clk, output reg [7:0] leds); +module top(input clk, rst, output reg [7:0] leds); -reg [25:0] ctr; +reg [7:0] ctr; always @(posedge clk) - ctr <= ctr + 1'b1; + if (rst) + ctr <= 8'h00; + else + ctr <= ctr + 1'b1; -assign leds = ctr[25:18]; +assign leds = ctr; -endmodule
\ No newline at end of file +endmodule diff --git a/generic/examples/blinky_tb.v b/generic/examples/blinky_tb.v new file mode 100644 index 00000000..f9925e6f --- /dev/null +++ b/generic/examples/blinky_tb.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +module blinky_tb; + +reg clk = 1'b0, rst = 1'b0; +reg [7:0] ctr_gold = 8'h00; +wire [7:0] ctr_gate; +top dut_i(.clk(clk), .rst(rst), .leds(ctr_gate)); + +task oneclk; + begin + clk = 1'b1; + #10; + clk = 1'b0; + #10; + end +endtask + +initial begin + $dumpfile("blinky_simtest.vcd"); + $dumpvars(0, blinky_tb); + #100; + rst = 1'b1; + repeat (5) oneclk; + #5 + rst = 1'b0; + #5 + repeat (500) begin + if (ctr_gold !== ctr_gate) begin + $display("mismatch gold=%b gate=%b", ctr_gold, ctr_gate); + $stop; + end + oneclk; + ctr_gold = ctr_gold + 1'b1; + end + $finish; +end + +endmodule diff --git a/generic/examples/simtest.sh b/generic/examples/simtest.sh new file mode 100755 index 00000000..ef328914 --- /dev/null +++ b/generic/examples/simtest.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -ex +yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v +${NEXTPNR:-../../nextpnr-generic} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json +yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v" +iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v +vvp -N ./blinky_simtest diff --git a/generic/synth/prims.v b/generic/synth/prims.v index 1148041c..ca445e6e 100644 --- a/generic/synth/prims.v +++ b/generic/synth/prims.v @@ -2,18 +2,27 @@ module LUT #( parameter K = 4, - parameter [2**K-1:0] INIT = 0, + parameter [2**K-1:0] INIT = 0 ) ( input [K-1:0] I, output Q ); - assign Q = INIT[I]; + wire [K-1:0] I_pd; + + genvar ii; + generate + for (ii = 0; ii < K; ii = ii + 1'b1) + assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii]; + endgenerate + + assign Q = INIT[I_pd]; endmodule module DFF ( input CLK, D, output reg Q ); + initial Q = 1'b0; always @(posedge CLK) Q <= D; endmodule |