diff options
| -rw-r--r-- | ecp5/constids.inc | 6 | ||||
| -rw-r--r-- | ecp5/gfx.cc | 4 | ||||
| -rw-r--r-- | ecp5/gfx.h | 508 |
3 files changed, 498 insertions, 20 deletions
diff --git a/ecp5/constids.inc b/ecp5/constids.inc index 656dd1b7..37577125 100644 --- a/ecp5/constids.inc +++ b/ecp5/constids.inc @@ -1301,10 +1301,14 @@ X(WIRE_TYPE_DQS) X(WIRE_TYPE_IOLOGIC) X(WIRE_TYPE_SIOLOGIC) X(WIRE_TYPE_PIO) -X(WIRE_TYPE_DDRDLL) X(WIRE_TYPE_EBR) X(WIRE_TYPE_MULT18) X(WIRE_TYPE_ALU54) +X(WIRE_TYPE_DDRDLL) +X(WIRE_TYPE_CCLK) +X(WIRE_TYPE_EXTREF) +X(WIRE_TYPE_DCU) + X(WIRE_TYPE_H00) X(WIRE_TYPE_H01) X(WIRE_TYPE_H02) diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc index 188e44ab..e06bcfa6 100644 --- a/ecp5/gfx.cc +++ b/ecp5/gfx.cc @@ -70,8 +70,8 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS el.type = GraphicElement::TYPE_LINE; el.style = style; bool top_bottom = (y == 0 || y == (h - 1)); - int gap = 3-(tilewire - TILE_WIRE_PADDOD_PIO)/5; - int num = (tilewire - TILE_WIRE_PADDOD_PIO)%5; + int gap = 3-(tilewire - TILE_WIRE_PADDOD_PIO)/6; + int num = (tilewire - TILE_WIRE_PADDOD_PIO)%6; if (top_bottom) { el.x1 = x + io_cell_h_x1 + (gap + 2) * 0.10 + 0.0017f * (num + 1); el.x2 = el.x1; @@ -682,37 +682,25 @@ enum GfxTileWireId TILE_WIRE_JPADDID_PIO, TILE_WIRE_IOLDOD_PIO, TILE_WIRE_IOLTOD_PIO, + TILE_WIRE_INRDD_PIO, TILE_WIRE_PADDOC_PIO, TILE_WIRE_PADDTC_PIO, TILE_WIRE_JPADDIC_PIO, TILE_WIRE_IOLDOC_PIO, TILE_WIRE_IOLTOC_PIO, + TILE_WIRE_INRDC_PIO, TILE_WIRE_PADDOB_PIO, TILE_WIRE_PADDTB_PIO, TILE_WIRE_JPADDIB_PIO, TILE_WIRE_IOLDOB_PIO, TILE_WIRE_IOLTOB_PIO, + TILE_WIRE_INRDB_PIO, TILE_WIRE_PADDOA_PIO, TILE_WIRE_PADDTA_PIO, TILE_WIRE_JPADDIA_PIO, TILE_WIRE_IOLDOA_PIO, TILE_WIRE_IOLTOA_PIO, - - TILE_WIRE_DDRDEL_DDRDLL, - TILE_WIRE_JRST_DDRDLL, - TILE_WIRE_JCLK_DDRDLL, - TILE_WIRE_JUDDCNTLN_DDRDLL, - TILE_WIRE_JFREEZE_DDRDLL, - TILE_WIRE_JLOCK_DDRDLL, - TILE_WIRE_JDIVOSC_DDRDLL, - TILE_WIRE_JDCNTL0_DDRDLL, - TILE_WIRE_JDCNTL1_DDRDLL, - TILE_WIRE_JDCNTL2_DDRDLL, - TILE_WIRE_JDCNTL3_DDRDLL, - TILE_WIRE_JDCNTL4_DDRDLL, - TILE_WIRE_JDCNTL5_DDRDLL, - TILE_WIRE_JDCNTL6_DDRDLL, - TILE_WIRE_JDCNTL7_DDRDLL, + TILE_WIRE_INRDA_PIO, TILE_WIRE_JADA0_EBR, TILE_WIRE_JADB0_EBR, @@ -1579,7 +1567,493 @@ enum GfxTileWireId TILE_WIRE_JQ4, TILE_WIRE_JQ5, TILE_WIRE_JQ6, - TILE_WIRE_JQ7 + TILE_WIRE_JQ7, + + TILE_WIRE_DDRDEL_DDRDLL, + TILE_WIRE_JRST_DDRDLL, + TILE_WIRE_JCLK_DDRDLL, + TILE_WIRE_JUDDCNTLN_DDRDLL, + TILE_WIRE_JFREEZE_DDRDLL, + TILE_WIRE_JLOCK_DDRDLL, + TILE_WIRE_JDIVOSC_DDRDLL, + TILE_WIRE_JDCNTL0_DDRDLL, + TILE_WIRE_JDCNTL1_DDRDLL, + TILE_WIRE_JDCNTL2_DDRDLL, + TILE_WIRE_JDCNTL3_DDRDLL, + TILE_WIRE_JDCNTL4_DDRDLL, + TILE_WIRE_JDCNTL5_DDRDLL, + TILE_WIRE_JDCNTL6_DDRDLL, + TILE_WIRE_JDCNTL7_DDRDLL, + + TILE_WIRE_JPADDI_CCLK, + TILE_WIRE_JPADDO_CCLK, + TILE_WIRE_JPADDT_CCLK, + + TILE_WIRE_REFCLKP_EXTREF, + TILE_WIRE_REFCLKN_EXTREF, + TILE_WIRE_JREFCLKO_EXTREF, + + TILE_WIRE_CH0_RX_REFCLK_DCU, + TILE_WIRE_CH1_RX_REFCLK_DCU, + TILE_WIRE_D_REFCLKI_DCU, + TILE_WIRE_JD_SYNC_PULSE2ND_DCU, + TILE_WIRE_JD_TXBIT_CLKN_TO_ND_DCU, + TILE_WIRE_JD_TXBIT_CLKP_TO_ND_DCU, + TILE_WIRE_JD_TXPLL_LOL_TO_ND_DCU, + TILE_WIRE_JCH0_FF_RX_PCLK_DCU, + TILE_WIRE_JCH1_FF_RX_PCLK_DCU, + TILE_WIRE_JCH0_FF_TX_PCLK_DCU, + TILE_WIRE_JCH1_FF_TX_PCLK_DCU, + TILE_WIRE_JCH0_FFC_CDR_EN_BITSLIP_DCU, + TILE_WIRE_JCH0_FFC_DIV11_MODE_RX_DCU, + TILE_WIRE_JCH0_FFC_DIV11_MODE_TX_DCU, + TILE_WIRE_JCH0_FFC_EI_EN_DCU, + TILE_WIRE_JCH0_FFC_ENABLE_CGALIGN_DCU, + TILE_WIRE_JCH0_FFC_FB_LOOPBACK_DCU, + TILE_WIRE_JCH0_FFC_LANE_RX_RST_DCU, + TILE_WIRE_JCH0_FFC_LANE_TX_RST_DCU, + TILE_WIRE_JCH0_FFC_LDR_CORE2TX_EN_DCU, + TILE_WIRE_JCH0_FFC_PCIE_CT_DCU, + TILE_WIRE_JCH0_FFC_PCIE_DET_EN_DCU, + TILE_WIRE_JCH0_FFC_PFIFO_CLR_DCU, + TILE_WIRE_JCH0_FFC_RATE_MODE_RX_DCU, + TILE_WIRE_JCH0_FFC_RATE_MODE_TX_DCU, + TILE_WIRE_JCH0_FFC_RRST_DCU, + TILE_WIRE_JCH0_FFC_RXPWDNB_DCU, + TILE_WIRE_JCH0_FFC_RX_GEAR_MODE_DCU, + TILE_WIRE_JCH0_FFC_SB_INV_RX_DCU, + TILE_WIRE_JCH0_FFC_SB_PFIFO_LP_DCU, + TILE_WIRE_JCH0_FFC_SIGNAL_DETECT_DCU, + TILE_WIRE_JCH0_FFC_TXPWDNB_DCU, + TILE_WIRE_JCH0_FFC_TX_GEAR_MODE_DCU, + TILE_WIRE_JCH0_FF_EBRD_CLK_DCU, + TILE_WIRE_JCH0_FF_RXI_CLK_DCU, + TILE_WIRE_JCH0_FF_TXI_CLK_DCU, + TILE_WIRE_JCH0_FF_TX_D_0_DCU, + TILE_WIRE_JCH0_FF_TX_D_10_DCU, + TILE_WIRE_JCH0_FF_TX_D_11_DCU, + TILE_WIRE_JCH0_FF_TX_D_12_DCU, + TILE_WIRE_JCH0_FF_TX_D_13_DCU, + TILE_WIRE_JCH0_FF_TX_D_14_DCU, + TILE_WIRE_JCH0_FF_TX_D_15_DCU, + TILE_WIRE_JCH0_FF_TX_D_16_DCU, + TILE_WIRE_JCH0_FF_TX_D_17_DCU, + TILE_WIRE_JCH0_FF_TX_D_18_DCU, + TILE_WIRE_JCH0_FF_TX_D_19_DCU, + TILE_WIRE_JCH0_FF_TX_D_1_DCU, + TILE_WIRE_JCH0_FF_TX_D_20_DCU, + TILE_WIRE_JCH0_FF_TX_D_21_DCU, + TILE_WIRE_JCH0_FF_TX_D_22_DCU, + TILE_WIRE_JCH0_FF_TX_D_23_DCU, + TILE_WIRE_JCH0_FF_TX_D_2_DCU, + TILE_WIRE_JCH0_FF_TX_D_3_DCU, + TILE_WIRE_JCH0_FF_TX_D_4_DCU, + TILE_WIRE_JCH0_FF_TX_D_5_DCU, + TILE_WIRE_JCH0_FF_TX_D_6_DCU, + TILE_WIRE_JCH0_FF_TX_D_7_DCU, + TILE_WIRE_JCH0_FF_TX_D_8_DCU, + TILE_WIRE_JCH0_FF_TX_D_9_DCU, + TILE_WIRE_JCH0_HDINN_DCU, + TILE_WIRE_JCH0_HDINP_DCU, + TILE_WIRE_JCH0_LDR_CORE2TX_DCU, + TILE_WIRE_JCH0_SCIEN_DCU, + TILE_WIRE_JCH0_SCISEL_DCU, + TILE_WIRE_JCH1_FFC_CDR_EN_BITSLIP_DCU, + TILE_WIRE_JCH1_FFC_DIV11_MODE_RX_DCU, + TILE_WIRE_JCH1_FFC_DIV11_MODE_TX_DCU, + TILE_WIRE_JCH1_FFC_EI_EN_DCU, + TILE_WIRE_JCH1_FFC_ENABLE_CGALIGN_DCU, + TILE_WIRE_JCH1_FFC_FB_LOOPBACK_DCU, + TILE_WIRE_JCH1_FFC_LANE_RX_RST_DCU, + TILE_WIRE_JCH1_FFC_LANE_TX_RST_DCU, + TILE_WIRE_JCH1_FFC_LDR_CORE2TX_EN_DCU, + TILE_WIRE_JCH1_FFC_PCIE_CT_DCU, + TILE_WIRE_JCH1_FFC_PCIE_DET_EN_DCU, + TILE_WIRE_JCH1_FFC_PFIFO_CLR_DCU, + TILE_WIRE_JCH1_FFC_RATE_MODE_RX_DCU, + TILE_WIRE_JCH1_FFC_RATE_MODE_TX_DCU, + TILE_WIRE_JCH1_FFC_RRST_DCU, + TILE_WIRE_JCH1_FFC_RXPWDNB_DCU, + TILE_WIRE_JCH1_FFC_RX_GEAR_MODE_DCU, + TILE_WIRE_JCH1_FFC_SB_INV_RX_DCU, + TILE_WIRE_JCH1_FFC_SB_PFIFO_LP_DCU, + TILE_WIRE_JCH1_FFC_SIGNAL_DETECT_DCU, + TILE_WIRE_JCH1_FFC_TXPWDNB_DCU, + TILE_WIRE_JCH1_FFC_TX_GEAR_MODE_DCU, + TILE_WIRE_JCH1_FF_EBRD_CLK_DCU, + TILE_WIRE_JCH1_FF_RXI_CLK_DCU, + TILE_WIRE_JCH1_FF_TXI_CLK_DCU, + TILE_WIRE_JCH1_FF_TX_D_0_DCU, + TILE_WIRE_JCH1_FF_TX_D_10_DCU, + TILE_WIRE_JCH1_FF_TX_D_11_DCU, + TILE_WIRE_JCH1_FF_TX_D_12_DCU, + TILE_WIRE_JCH1_FF_TX_D_13_DCU, + TILE_WIRE_JCH1_FF_TX_D_14_DCU, + TILE_WIRE_JCH1_FF_TX_D_15_DCU, + TILE_WIRE_JCH1_FF_TX_D_16_DCU, + TILE_WIRE_JCH1_FF_TX_D_17_DCU, + TILE_WIRE_JCH1_FF_TX_D_18_DCU, + TILE_WIRE_JCH1_FF_TX_D_19_DCU, + TILE_WIRE_JCH1_FF_TX_D_1_DCU, + TILE_WIRE_JCH1_FF_TX_D_20_DCU, + TILE_WIRE_JCH1_FF_TX_D_21_DCU, + TILE_WIRE_JCH1_FF_TX_D_22_DCU, + TILE_WIRE_JCH1_FF_TX_D_23_DCU, + TILE_WIRE_JCH1_FF_TX_D_2_DCU, + TILE_WIRE_JCH1_FF_TX_D_3_DCU, + TILE_WIRE_JCH1_FF_TX_D_4_DCU, + TILE_WIRE_JCH1_FF_TX_D_5_DCU, + TILE_WIRE_JCH1_FF_TX_D_6_DCU, + TILE_WIRE_JCH1_FF_TX_D_7_DCU, + TILE_WIRE_JCH1_FF_TX_D_8_DCU, + TILE_WIRE_JCH1_FF_TX_D_9_DCU, + TILE_WIRE_JCH1_HDINN_DCU, + TILE_WIRE_JCH1_HDINP_DCU, + TILE_WIRE_JCH1_LDR_CORE2TX_DCU, + TILE_WIRE_JCH1_SCIEN_DCU, + TILE_WIRE_JCH1_SCISEL_DCU, + TILE_WIRE_JD_CIN0_DCU, + TILE_WIRE_JD_CIN10_DCU, + TILE_WIRE_JD_CIN11_DCU, + TILE_WIRE_JD_CIN1_DCU, + TILE_WIRE_JD_CIN2_DCU, + TILE_WIRE_JD_CIN3_DCU, + TILE_WIRE_JD_CIN4_DCU, + TILE_WIRE_JD_CIN5_DCU, + TILE_WIRE_JD_CIN6_DCU, + TILE_WIRE_JD_CIN7_DCU, + TILE_WIRE_JD_CIN8_DCU, + TILE_WIRE_JD_CIN9_DCU, + TILE_WIRE_JD_CYAWSTN_DCU, + TILE_WIRE_JD_FFC_DUAL_RST_DCU, + TILE_WIRE_JD_FFC_MACROPDB_DCU, + TILE_WIRE_JD_FFC_MACRO_RST_DCU, + TILE_WIRE_JD_FFC_SYNC_TOGGLE_DCU, + TILE_WIRE_JD_FFC_TRST_DCU, + TILE_WIRE_JD_SCAN_ENABLE_DCU, + TILE_WIRE_JD_SCAN_IN_0_DCU, + TILE_WIRE_JD_SCAN_IN_1_DCU, + TILE_WIRE_JD_SCAN_IN_2_DCU, + TILE_WIRE_JD_SCAN_IN_3_DCU, + TILE_WIRE_JD_SCAN_IN_4_DCU, + TILE_WIRE_JD_SCAN_IN_5_DCU, + TILE_WIRE_JD_SCAN_IN_6_DCU, + TILE_WIRE_JD_SCAN_IN_7_DCU, + TILE_WIRE_JD_SCAN_MODE_DCU, + TILE_WIRE_JD_SCAN_RESET_DCU, + TILE_WIRE_JD_SCIADDR0_DCU, + TILE_WIRE_JD_SCIADDR1_DCU, + TILE_WIRE_JD_SCIADDR2_DCU, + TILE_WIRE_JD_SCIADDR3_DCU, + TILE_WIRE_JD_SCIADDR4_DCU, + TILE_WIRE_JD_SCIADDR5_DCU, + TILE_WIRE_JD_SCIENAUX_DCU, + TILE_WIRE_JD_SCIRD_DCU, + TILE_WIRE_JD_SCISELAUX_DCU, + TILE_WIRE_JD_SCIWDATA0_DCU, + TILE_WIRE_JD_SCIWDATA1_DCU, + TILE_WIRE_JD_SCIWDATA2_DCU, + TILE_WIRE_JD_SCIWDATA3_DCU, + TILE_WIRE_JD_SCIWDATA4_DCU, + TILE_WIRE_JD_SCIWDATA5_DCU, + TILE_WIRE_JD_SCIWDATA6_DCU, + TILE_WIRE_JD_SCIWDATA7_DCU, + TILE_WIRE_JD_SCIWSTN_DCU, + TILE_WIRE_JCH0_HDOUTN_DCU, + TILE_WIRE_JCH1_HDOUTN_DCU, + TILE_WIRE_JCH0_HDOUTP_DCU, + TILE_WIRE_JCH1_HDOUTP_DCU, + TILE_WIRE_JCH1_FF_RX_D_16_DCU, + TILE_WIRE_JCH1_FF_RX_D_17_DCU, + TILE_WIRE_JCH1_FF_RX_D_18_DCU, + TILE_WIRE_JCH1_FF_RX_D_19_DCU, + TILE_WIRE_JCH1_FF_RX_D_20_DCU, + TILE_WIRE_JCH1_FF_RX_D_21_DCU, + TILE_WIRE_JCH1_FF_RX_D_22_DCU, + TILE_WIRE_JCH1_FF_RX_D_23_DCU, + TILE_WIRE_JCH1_FFS_SKP_DELETED_DCU, + TILE_WIRE_JCH1_FFS_SKP_ADDED_DCU, + TILE_WIRE_JCH1_LDR_RX2CORE_DCU, + TILE_WIRE_JD_SCAN_OUT_7_DCU, + TILE_WIRE_JCH1_FFS_TXFBFIFO_ERROR_DCU, + TILE_WIRE_JCH1_FFS_PCIE_CON_DCU, + TILE_WIRE_JCH1_FFS_PCIE_DONE_DCU, + TILE_WIRE_JD_SCAN_OUT_3_DCU, + TILE_WIRE_JD_COUT1_DCU, + TILE_WIRE_JD_SCAN_OUT_0_DCU, + TILE_WIRE_JD_FFS_PLOL_DCU, + TILE_WIRE_JCH0_FF_RX_D_0_DCU, + TILE_WIRE_JCH0_FF_RX_D_1_DCU, + TILE_WIRE_JCH0_FF_RX_D_2_DCU, + TILE_WIRE_JCH0_FF_RX_D_3_DCU, + TILE_WIRE_JCH0_FF_RX_D_4_DCU, + TILE_WIRE_JCH0_FF_RX_D_5_DCU, + TILE_WIRE_JCH0_FF_RX_D_6_DCU, + TILE_WIRE_JCH0_FF_RX_D_7_DCU, + TILE_WIRE_JCH0_FFS_CC_OVERRUN_DCU, + TILE_WIRE_JCH0_FFS_RLOL_DCU, + TILE_WIRE_JCH0_FF_RX_D_8_DCU, + TILE_WIRE_JCH0_FF_RX_D_9_DCU, + TILE_WIRE_JCH0_FF_RX_D_10_DCU, + TILE_WIRE_JCH0_FF_RX_D_11_DCU, + TILE_WIRE_JCH0_FF_RX_D_12_DCU, + TILE_WIRE_JCH0_FF_RX_D_13_DCU, + TILE_WIRE_JCH0_FF_RX_D_14_DCU, + TILE_WIRE_JCH0_FF_RX_D_15_DCU, + TILE_WIRE_JCH0_FFS_RLOS_DCU, + TILE_WIRE_JCH0_FFS_LS_SYNC_STATUS_DCU, + TILE_WIRE_JCH0_FF_RX_D_16_DCU, + TILE_WIRE_JCH0_FF_RX_D_17_DCU, + TILE_WIRE_JCH0_FF_RX_D_18_DCU, + TILE_WIRE_JCH0_FF_RX_D_19_DCU, + TILE_WIRE_JCH0_FF_RX_D_20_DCU, + TILE_WIRE_JCH0_FF_RX_D_21_DCU, + TILE_WIRE_JCH0_FF_RX_D_22_DCU, + TILE_WIRE_JCH0_FF_RX_D_23_DCU, + TILE_WIRE_JCH0_FF_RX_F_CLK_DCU, + TILE_WIRE_JCH0_FF_RX_H_CLK_DCU, + TILE_WIRE_JD_COUT19_DCU, + TILE_WIRE_JD_COUT16_DCU, + TILE_WIRE_JD_COUT6_DCU, + TILE_WIRE_JD_COUT7_DCU, + TILE_WIRE_JD_COUT8_DCU, + TILE_WIRE_JD_COUT9_DCU, + TILE_WIRE_JD_COUT10_DCU, + TILE_WIRE_JD_COUT17_DCU, + TILE_WIRE_JD_COUT18_DCU, + TILE_WIRE_JCH0_FFS_CC_UNDERRUN_DCU, + TILE_WIRE_JCH0_FFS_RXFBFIFO_ERROR_DCU, + TILE_WIRE_JD_COUT11_DCU, + TILE_WIRE_JD_COUT12_DCU, + TILE_WIRE_JD_COUT13_DCU, + TILE_WIRE_JD_COUT14_DCU, + TILE_WIRE_JD_COUT15_DCU, + TILE_WIRE_JD_COUT0_DCU, + TILE_WIRE_JD_COUT2_DCU, + TILE_WIRE_JD_COUT3_DCU, + TILE_WIRE_JD_COUT4_DCU, + TILE_WIRE_JD_COUT5_DCU, + TILE_WIRE_JD_SCAN_OUT_6_DCU, + TILE_WIRE_JD_SCIINT_DCU, + TILE_WIRE_JD_SCIRDATA0_DCU, + TILE_WIRE_JD_SCIRDATA1_DCU, + TILE_WIRE_JD_SCIRDATA2_DCU, + TILE_WIRE_JD_SCIRDATA3_DCU, + TILE_WIRE_JD_SCIRDATA4_DCU, + TILE_WIRE_JD_SCIRDATA5_DCU, + TILE_WIRE_JD_SCIRDATA6_DCU, + TILE_WIRE_JD_SCIRDATA7_DCU, + TILE_WIRE_JCH1_FF_RX_F_CLK_DCU, + TILE_WIRE_JCH1_FF_RX_H_CLK_DCU, + TILE_WIRE_JCH1_FFS_RXFBFIFO_ERROR_DCU, + TILE_WIRE_JCH1_FFS_CC_UNDERRUN_DCU, + TILE_WIRE_JCH1_FFS_LS_SYNC_STATUS_DCU, + TILE_WIRE_JCH1_FFS_RLOS_DCU, + TILE_WIRE_JCH1_FFS_RLOL_DCU, + TILE_WIRE_JCH1_FFS_CC_OVERRUN_DCU, + TILE_WIRE_JD_SCAN_OUT_4_DCU, + TILE_WIRE_JCH1_FF_TX_F_CLK_DCU, + TILE_WIRE_JCH1_FF_TX_H_CLK_DCU, + TILE_WIRE_JCH1_FF_RX_D_0_DCU, + TILE_WIRE_JCH1_FF_RX_D_1_DCU, + TILE_WIRE_JCH1_FF_RX_D_2_DCU, + TILE_WIRE_JCH1_FF_RX_D_3_DCU, + TILE_WIRE_JCH1_FF_RX_D_4_DCU, + TILE_WIRE_JCH1_FF_RX_D_5_DCU, + TILE_WIRE_JCH1_FF_RX_D_6_DCU, + TILE_WIRE_JCH1_FF_RX_D_7_DCU, + TILE_WIRE_JCH1_FF_RX_D_8_DCU, + TILE_WIRE_JCH1_FF_RX_D_9_DCU, + TILE_WIRE_JCH1_FF_RX_D_10_DCU, + TILE_WIRE_JCH1_FF_RX_D_11_DCU, + TILE_WIRE_JCH1_FF_RX_D_12_DCU, + TILE_WIRE_JCH1_FF_RX_D_13_DCU, + TILE_WIRE_JCH1_FF_RX_D_14_DCU, + TILE_WIRE_JCH1_FF_RX_D_15_DCU, + TILE_WIRE_JD_SCAN_OUT_1_DCU, + TILE_WIRE_JCH0_FFS_PCIE_DONE_DCU, + TILE_WIRE_JCH0_FFS_PCIE_CON_DCU, + TILE_WIRE_JD_SCAN_OUT_2_DCU, + TILE_WIRE_JCH0_FFS_TXFBFIFO_ERROR_DCU, + TILE_WIRE_JD_SCAN_OUT_5_DCU, + TILE_WIRE_JCH0_LDR_RX2CORE_DCU, + TILE_WIRE_JCH0_FFS_SKP_ADDED_DCU, + TILE_WIRE_JCH0_FF_TX_H_CLK_DCU, + TILE_WIRE_JCH0_FF_TX_F_CLK_DCU, + TILE_WIRE_JCH0_FFS_SKP_DELETED_DCU, + + TILE_WIRE_G_CLKI_BDCC0, + TILE_WIRE_G_JCE_BDCC0, + TILE_WIRE_G_CLKO_BDCC0, + TILE_WIRE_G_CLKI_BDCC1, + TILE_WIRE_G_JCE_BDCC1, + TILE_WIRE_G_CLKO_BDCC1, + TILE_WIRE_G_CLKI_BDCC2, + TILE_WIRE_G_JCE_BDCC2, + TILE_WIRE_G_CLKO_BDCC2, + TILE_WIRE_G_CLKI_BDCC3, + TILE_WIRE_G_JCE_BDCC3, + TILE_WIRE_G_CLKO_BDCC3, + TILE_WIRE_G_CLKI_BDCC4, + TILE_WIRE_G_JCE_BDCC4, + TILE_WIRE_G_CLKO_BDCC4, + TILE_WIRE_G_CLKI_BDCC5, + TILE_WIRE_G_JCE_BDCC5, + TILE_WIRE_G_CLKO_BDCC5, + TILE_WIRE_G_CLKI_BDCC6, + TILE_WIRE_G_JCE_BDCC6, + TILE_WIRE_G_CLKO_BDCC6, + TILE_WIRE_G_CLKI_BDCC7, + TILE_WIRE_G_JCE_BDCC7, + TILE_WIRE_G_CLKO_BDCC7, + TILE_WIRE_G_CLKI_BDCC8, + TILE_WIRE_G_JCE_BDCC8, + TILE_WIRE_G_CLKO_BDCC8, + TILE_WIRE_G_CLKI_BDCC9, + TILE_WIRE_G_JCE_BDCC9, + TILE_WIRE_G_CLKO_BDCC9, + TILE_WIRE_G_CLKI_BDCC10, + TILE_WIRE_G_JCE_BDCC10, + TILE_WIRE_G_CLKO_BDCC10, + TILE_WIRE_G_CLKI_BDCC11, + TILE_WIRE_G_JCE_BDCC11, + TILE_WIRE_G_CLKO_BDCC11, + TILE_WIRE_G_CLKI_BDCC12, + TILE_WIRE_G_JCE_BDCC12, + TILE_WIRE_G_CLKO_BDCC12, + TILE_WIRE_G_CLKI_BDCC13, + TILE_WIRE_G_JCE_BDCC13, + TILE_WIRE_G_CLKO_BDCC13, + TILE_WIRE_G_CLKI_BDCC14, + TILE_WIRE_G_JCE_BDCC14, + TILE_WIRE_G_CLKO_BDCC14, + TILE_WIRE_G_CLKI_BDCC15, + TILE_WIRE_G_JCE_BDCC15, + TILE_WIRE_G_CLKO_BDCC15, + + + TILE_WIRE_G_CLKI_TDCC0, + TILE_WIRE_G_JCE_TDCC0, + TILE_WIRE_G_CLKO_TDCC0, + TILE_WIRE_G_CLKI_TDCC1, + TILE_WIRE_G_JCE_TDCC1, + TILE_WIRE_G_CLKO_TDCC1, + TILE_WIRE_G_CLKI_TDCC2, + TILE_WIRE_G_JCE_TDCC2, + TILE_WIRE_G_CLKO_TDCC2, + TILE_WIRE_G_CLKI_TDCC3, + TILE_WIRE_G_JCE_TDCC3, + TILE_WIRE_G_CLKO_TDCC3, + TILE_WIRE_G_CLKI_TDCC4, + TILE_WIRE_G_JCE_TDCC4, + TILE_WIRE_G_CLKO_TDCC4, + TILE_WIRE_G_CLKI_TDCC5, + TILE_WIRE_G_JCE_TDCC5, + TILE_WIRE_G_CLKO_TDCC5, + TILE_WIRE_G_CLKI_TDCC6, + TILE_WIRE_G_JCE_TDCC6, + TILE_WIRE_G_CLKO_TDCC6, + TILE_WIRE_G_CLKI_TDCC7, + TILE_WIRE_G_JCE_TDCC7, + TILE_WIRE_G_CLKO_TDCC7, + TILE_WIRE_G_CLKI_TDCC8, + TILE_WIRE_G_JCE_TDCC8, + TILE_WIRE_G_CLKO_TDCC8, + TILE_WIRE_G_CLKI_TDCC9, + TILE_WIRE_G_JCE_TDCC9, + TILE_WIRE_G_CLKO_TDCC9, + TILE_WIRE_G_CLKI_TDCC10, + TILE_WIRE_G_JCE_TDCC10, + TILE_WIRE_G_CLKO_TDCC10, + TILE_WIRE_G_CLKI_TDCC11, + TILE_WIRE_G_JCE_TDCC11, + TILE_WIRE_G_CLKO_TDCC11, + + TILE_WIRE_G_CLKI_RDCC0, + TILE_WIRE_G_JCE_RDCC0, + TILE_WIRE_G_CLKO_RDCC0, + TILE_WIRE_G_CLKI_RDCC1, + TILE_WIRE_G_JCE_RDCC1, + TILE_WIRE_G_CLKO_RDCC1, + TILE_WIRE_G_CLKI_RDCC2, + TILE_WIRE_G_JCE_RDCC2, + TILE_WIRE_G_CLKO_RDCC2, + TILE_WIRE_G_CLKI_RDCC3, + TILE_WIRE_G_JCE_RDCC3, + TILE_WIRE_G_CLKO_RDCC3, + TILE_WIRE_G_CLKI_RDCC4, + TILE_WIRE_G_JCE_RDCC4, + TILE_WIRE_G_CLKO_RDCC4, + TILE_WIRE_G_CLKI_RDCC5, + TILE_WIRE_G_JCE_RDCC5, + TILE_WIRE_G_CLKO_RDCC5, + TILE_WIRE_G_CLKI_RDCC6, + TILE_WIRE_G_JCE_RDCC6, + TILE_WIRE_G_CLKO_RDCC6, + TILE_WIRE_G_CLKI_RDCC7, + TILE_WIRE_G_JCE_RDCC7, + TILE_WIRE_G_CLKO_RDCC7, + TILE_WIRE_G_CLKI_RDCC8, + TILE_WIRE_G_JCE_RDCC8, + TILE_WIRE_G_CLKO_RDCC8, + TILE_WIRE_G_CLKI_RDCC9, + TILE_WIRE_G_JCE_RDCC9, + TILE_WIRE_G_CLKO_RDCC9, + TILE_WIRE_G_CLKI_RDCC10, + TILE_WIRE_G_JCE_RDCC10, + TILE_WIRE_G_CLKO_RDCC10, + TILE_WIRE_G_CLKI_RDCC11, + TILE_WIRE_G_JCE_RDCC11, + TILE_WIRE_G_CLKO_RDCC11, + TILE_WIRE_G_CLKI_RDCC12, + TILE_WIRE_G_JCE_RDCC12, + TILE_WIRE_G_CLKO_RDCC12, + TILE_WIRE_G_CLKI_RDCC13, + TILE_WIRE_G_JCE_RDCC13, + TILE_WIRE_G_CLKO_RDCC13, + + TILE_WIRE_G_CLKI_LDCC0, + TILE_WIRE_G_JCE_LDCC0, + TILE_WIRE_G_CLKO_LDCC0, + TILE_WIRE_G_CLKI_LDCC1, + TILE_WIRE_G_JCE_LDCC1, + TILE_WIRE_G_CLKO_LDCC1, + TILE_WIRE_G_CLKI_LDCC2, + TILE_WIRE_G_JCE_LDCC2, + TILE_WIRE_G_CLKO_LDCC2, + TILE_WIRE_G_CLKI_LDCC3, + TILE_WIRE_G_JCE_LDCC3, + TILE_WIRE_G_CLKO_LDCC3, + TILE_WIRE_G_CLKI_LDCC4, + TILE_WIRE_G_JCE_LDCC4, + TILE_WIRE_G_CLKO_LDCC4, + TILE_WIRE_G_CLKI_LDCC5, + TILE_WIRE_G_JCE_LDCC5, + TILE_WIRE_G_CLKO_LDCC5, + TILE_WIRE_G_CLKI_LDCC6, + TILE_WIRE_G_JCE_LDCC6, + TILE_WIRE_G_CLKO_LDCC6, + TILE_WIRE_G_CLKI_LDCC7, + TILE_WIRE_G_JCE_LDCC7, + TILE_WIRE_G_CLKO_LDCC7, + TILE_WIRE_G_CLKI_LDCC8, + TILE_WIRE_G_JCE_LDCC8, + TILE_WIRE_G_CLKO_LDCC8, + TILE_WIRE_G_CLKI_LDCC9, + TILE_WIRE_G_JCE_LDCC9, + TILE_WIRE_G_CLKO_LDCC9, + TILE_WIRE_G_CLKI_LDCC10, + TILE_WIRE_G_JCE_LDCC10, + TILE_WIRE_G_CLKO_LDCC10, + TILE_WIRE_G_CLKI_LDCC11, + TILE_WIRE_G_JCE_LDCC11, + TILE_WIRE_G_CLKO_LDCC11, + TILE_WIRE_G_CLKI_LDCC12, + TILE_WIRE_G_JCE_LDCC12, + TILE_WIRE_G_CLKO_LDCC12, + TILE_WIRE_G_CLKI_LDCC13, + TILE_WIRE_G_JCE_LDCC13, + TILE_WIRE_G_CLKO_LDCC13 }; |