Added BUILD_GUI, BUILD_PYTHON and BUILD_TESTS cmake options,

6 files changed, 132 insertions, 132 deletions

diff --git a/tests/ice40/hx1k.cc b/tests/ice40/hx1k.cc
index e1734fce..1d212f6a 100644
--- a/tests/ice40/hx1k.cc
+++ b/tests/ice40/hx1k.cc
@@ -9,23 +9,23 @@ class HX1KTest : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::HX1K;
+        chipArgs.type = ArchArgs::HX1K;
         chipArgs.package = "tq144";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(HX1KTest, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 1416);
@@ -34,9 +34,9 @@ TEST_F(HX1KTest, bel_names)
 TEST_F(HX1KTest, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 27682);
@@ -45,9 +45,9 @@ TEST_F(HX1KTest, wire_names)
 TEST_F(HX1KTest, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 319904);
@@ -55,11 +55,11 @@ TEST_F(HX1KTest, pip_names)
 
 TEST_F(HX1KTest, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(HX1KTest, uphill_to_downhill)
 
 TEST_F(HX1KTest, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;
diff --git a/tests/ice40/hx8k.cc b/tests/ice40/hx8k.cc
index 201dbdc2..eef5eb7c 100644
--- a/tests/ice40/hx8k.cc
+++ b/tests/ice40/hx8k.cc
@@ -9,23 +9,23 @@ class HX8KTest : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::HX8K;
+        chipArgs.type = ArchArgs::HX8K;
         chipArgs.package = "ct256";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(HX8KTest, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 7968);
@@ -34,9 +34,9 @@ TEST_F(HX8KTest, bel_names)
 TEST_F(HX8KTest, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 135174);
@@ -45,9 +45,9 @@ TEST_F(HX8KTest, wire_names)
 TEST_F(HX8KTest, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 1652480);
@@ -55,11 +55,11 @@ TEST_F(HX8KTest, pip_names)
 
 TEST_F(HX8KTest, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(HX8KTest, uphill_to_downhill)
 
 TEST_F(HX8KTest, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;
diff --git a/tests/ice40/lp1k.cc b/tests/ice40/lp1k.cc
index 6afc8c9e..392cf5c6 100644
--- a/tests/ice40/lp1k.cc
+++ b/tests/ice40/lp1k.cc
@@ -9,23 +9,23 @@ class LP1KTest : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::LP1K;
+        chipArgs.type = ArchArgs::LP1K;
         chipArgs.package = "tq144";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(LP1KTest, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 1416);
@@ -34,9 +34,9 @@ TEST_F(LP1KTest, bel_names)
 TEST_F(LP1KTest, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 27682);
@@ -45,9 +45,9 @@ TEST_F(LP1KTest, wire_names)
 TEST_F(LP1KTest, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 319904);
@@ -55,11 +55,11 @@ TEST_F(LP1KTest, pip_names)
 
 TEST_F(LP1KTest, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(LP1KTest, uphill_to_downhill)
 
 TEST_F(LP1KTest, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;
diff --git a/tests/ice40/lp384.cc b/tests/ice40/lp384.cc
index 77b82951..f54683f6 100644
--- a/tests/ice40/lp384.cc
+++ b/tests/ice40/lp384.cc
@@ -9,23 +9,23 @@ class LP384Test : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::LP384;
+        chipArgs.type = ArchArgs::LP384;
         chipArgs.package = "qn32";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(LP384Test, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 440);
@@ -34,9 +34,9 @@ TEST_F(LP384Test, bel_names)
 TEST_F(LP384Test, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 8294);
@@ -45,9 +45,9 @@ TEST_F(LP384Test, wire_names)
 TEST_F(LP384Test, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 86864);
@@ -55,11 +55,11 @@ TEST_F(LP384Test, pip_names)
 
 TEST_F(LP384Test, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(LP384Test, uphill_to_downhill)
 
 TEST_F(LP384Test, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;
diff --git a/tests/ice40/lp8k.cc b/tests/ice40/lp8k.cc
index 06543fd8..940e1c20 100644
--- a/tests/ice40/lp8k.cc
+++ b/tests/ice40/lp8k.cc
@@ -9,23 +9,23 @@ class LP8KTest : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::LP8K;
+        chipArgs.type = ArchArgs::LP8K;
         chipArgs.package = "ct256";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(LP8KTest, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 7968);
@@ -34,9 +34,9 @@ TEST_F(LP8KTest, bel_names)
 TEST_F(LP8KTest, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 135174);
@@ -45,9 +45,9 @@ TEST_F(LP8KTest, wire_names)
 TEST_F(LP8KTest, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 1652480);
@@ -55,11 +55,11 @@ TEST_F(LP8KTest, pip_names)
 
 TEST_F(LP8KTest, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(LP8KTest, uphill_to_downhill)
 
 TEST_F(LP8KTest, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;
diff --git a/tests/ice40/up5k.cc b/tests/ice40/up5k.cc
index 93d5f8a2..f6a58b3a 100644
--- a/tests/ice40/up5k.cc
+++ b/tests/ice40/up5k.cc
@@ -9,23 +9,23 @@ class UP5KTest : public ::testing::Test
   protected:
     virtual void SetUp()
     {
-        chipArgs.type = ChipArgs::UP5K;
+        chipArgs.type = ArchArgs::UP5K;
         chipArgs.package = "sg48";
-        design = new Design(chipArgs);
+        ctx = new Context(chipArgs);
     }
 
-    virtual void TearDown() { delete design; }
+    virtual void TearDown() { delete ctx; }
 
-    ChipArgs chipArgs;
-    Design *design;
+    ArchArgs chipArgs;
+    Context *ctx;
 };
 
 TEST_F(UP5KTest, bel_names)
 {
     int bel_count = 0;
-    for (auto bel : design->chip.getBels()) {
-        auto name = design->chip.getBelName(bel);
-        ASSERT_EQ(bel, design->chip.getBelByName(name));
+    for (auto bel : ctx->getBels()) {
+        auto name = ctx->getBelName(bel);
+        ASSERT_EQ(bel, ctx->getBelByName(name));
         bel_count++;
     }
     ASSERT_EQ(bel_count, 5414);
@@ -34,9 +34,9 @@ TEST_F(UP5KTest, bel_names)
 TEST_F(UP5KTest, wire_names)
 {
     int wire_count = 0;
-    for (auto wire : design->chip.getWires()) {
-        auto name = design->chip.getWireName(wire);
-        assert(wire == design->chip.getWireByName(name));
+    for (auto wire : ctx->getWires()) {
+        auto name = ctx->getWireName(wire);
+        assert(wire == ctx->getWireByName(name));
         wire_count++;
     }
     ASSERT_EQ(wire_count, 103383);
@@ -45,9 +45,9 @@ TEST_F(UP5KTest, wire_names)
 TEST_F(UP5KTest, pip_names)
 {
     int pip_count = 0;
-    for (auto pip : design->chip.getPips()) {
-        auto name = design->chip.getPipName(pip);
-        assert(pip == design->chip.getPipByName(name));
+    for (auto pip : ctx->getPips()) {
+        auto name = ctx->getPipName(pip);
+        assert(pip == ctx->getPipByName(name));
         pip_count++;
     }
     ASSERT_EQ(pip_count, 1219104);
@@ -55,11 +55,11 @@ TEST_F(UP5KTest, pip_names)
 
 TEST_F(UP5KTest, uphill_to_downhill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto uphill_pip : design->chip.getPipsUphill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto uphill_pip : ctx->getPipsUphill(dst)) {
             bool found_downhill = false;
-            for (auto downhill_pip : design->chip.getPipsDownhill(
-                         design->chip.getPipSrcWire(uphill_pip))) {
+            for (auto downhill_pip : ctx->getPipsDownhill(
+                         ctx->getPipSrcWire(uphill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_downhill);
                     found_downhill = true;
@@ -72,11 +72,11 @@ TEST_F(UP5KTest, uphill_to_downhill)
 
 TEST_F(UP5KTest, downhill_to_uphill)
 {
-    for (auto dst : design->chip.getWires()) {
-        for (auto downhill_pip : design->chip.getPipsDownhill(dst)) {
+    for (auto dst : ctx->getWires()) {
+        for (auto downhill_pip : ctx->getPipsDownhill(dst)) {
             bool found_uphill = false;
-            for (auto uphill_pip : design->chip.getPipsUphill(
-                         design->chip.getPipDstWire(downhill_pip))) {
+            for (auto uphill_pip : ctx->getPipsUphill(
+                         ctx->getPipDstWire(downhill_pip))) {
                 if (uphill_pip == downhill_pip) {
                     ASSERT_FALSE(found_uphill);
                     found_uphill = true;