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| author | gatecat <gatecat@ds0.me> | 2021-02-25 10:22:45 +0000 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-25 10:22:45 +0000 | 
| commit | ab8dfcfba4544c6733d074b24b0529d431b66d29 (patch) | |
| tree | af212992fee7cd0a8fb27d19d0137587402fdc1b /python | |
| parent | e2cdaa653c805f9bfb6f0ab36295858e5dd3179d (diff) | |
| parent | a30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 (diff) | |
| download | nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.gz nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.bz2 nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.zip  | |
Merge pull request #591 from litghost/add_constant_network
Add constant network support to FPGA interchange arch
Diffstat (limited to 'python')
| -rw-r--r-- | python/check_arch_api.py | 51 | 
1 files changed, 42 insertions, 9 deletions
diff --git a/python/check_arch_api.py b/python/check_arch_api.py index 647faefc..166f1fd3 100644 --- a/python/check_arch_api.py +++ b/python/check_arch_api.py @@ -18,6 +18,11 @@ pin connectivity tests. Example test_data.yaml:  pip_test:      - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3        dst_wire: SLICE_X15Y93.SLICEL/D3 +pip_chain_test: +    - wires: +        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE +        - $CONSTANTS_X0Y0/$GND_NODE +        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE  bel_pin_test:      - bel: SLICE_X15Y93.SLICEL/D6LUT        pin: A3 @@ -25,25 +30,48 @@ bel_pin_test:  """  import yaml +import sys + +  def check_arch_api(ctx): +    success = True      pips_tested = 0 +    pips_failed = 0 + +    def test_pip(src_wire_name, dst_wire_name): +        nonlocal success +        nonlocal pips_tested +        nonlocal pips_failed + +        pip = None +        for pip_name in ctx.getPipsDownhill(src_wire_name): +            if ctx.getPipDstWire(pip_name) == dst_wire_name: +                pip = pip_name +                src_wire = ctx.getPipSrcWire(pip_name) +                assert src_wire == src_wire_name, ( +                        src_wire, src_wire_name) + + +        if pip is None: +            success = False +            pips_failed += 1 +            print('Pip from {} to {} failed'.format(src_wire_name, dst_wire_name)) +        else: +            pips_tested += 1      bel_pins_tested = 0      with open('test_data.yaml', 'r') as f:          test_data = yaml.safe_load(f.read())          if 'pip_test' in test_data:              for pip_test in test_data['pip_test']: -                pip = None -                for pip_name in ctx.getPipsDownhill(pip_test['src_wire']): -                    if ctx.getPipDstWire(pip_name) == pip_test['dst_wire']: -                        pip = pip_name -                        src_wire = ctx.getPipSrcWire(pip_name) -                        assert src_wire == pip_test['src_wire'], ( -                                src_wire, pip_test['src_wire']) +                test_pip(pip_test['src_wire'], pip_test['dst_wire']) -                assert pip is not None -                pips_tested += 1 +        if 'pip_chain_test' in test_data: +            for chain_test in test_data['pip_chain_test']: +                wires = chain_test['wires'] +                for src_wire, dst_wire in zip(wires, wires[1:]): +                    test_pip(src_wire, dst_wire)          if 'bel_pin_test' in test_data:              for bel_pin_test in test_data['bel_pin_test']: @@ -54,4 +82,9 @@ def check_arch_api(ctx):      print('Tested {} pips and {} bel pins'.format(pips_tested, bel_pins_tested)) +    if not success: +        print('{} pips failed'.format(pips_failed)) +        sys.exit(-1) + +  check_arch_api(ctx)  | 
