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| author | Lofty <dan.ravensloft@gmail.com> | 2022-01-18 12:15:01 +0000 |
|---|---|---|
| committer | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 17:13:54 +0000 |
| commit | 9be65cd67c6a40ddc35460b97a014bbcd0af2f85 (patch) | |
| tree | 63f23c9257b169be08613bd1304cb03b55f76907 /mistral | |
| parent | da65afc83b83f02efa96e9a7735f7044a1f1e6d1 (diff) | |
| download | nextpnr-9be65cd67c6a40ddc35460b97a014bbcd0af2f85.tar.gz nextpnr-9be65cd67c6a40ddc35460b97a014bbcd0af2f85.tar.bz2 nextpnr-9be65cd67c6a40ddc35460b97a014bbcd0af2f85.zip | |
mistral: some more M10K fixes
Diffstat (limited to 'mistral')
| -rw-r--r-- | mistral/bitstream.cc | 4 | ||||
| -rw-r--r-- | mistral/pack.cc | 8 |
2 files changed, 5 insertions, 7 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 3490a3d7..660e3671 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -126,7 +126,7 @@ struct MistralBitgen // DATA_FLOW_THRU is probably transparent reads. cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1); - cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64()); + cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64()); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1); @@ -135,7 +135,7 @@ struct MistralBitgen cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1); - cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64()); + cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64()); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1); diff --git a/mistral/pack.cc b/mistral/pack.cc index 09fedf10..27ad3c92 100644 --- a/mistral/pack.cc +++ b/mistral/pack.cc @@ -399,9 +399,9 @@ struct MistralPacker // It *does* generate ACLR[01] but leaves them unconnected if unused. // Enables. - // RDEN[0] and WREN[1] are left unconnected. - ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")}; - ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")}; + // RDEN[1] and WREN[0] are left unconnected. + ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")}; + ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("RDEN[0]")}; // Clocks. ci->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")}; @@ -451,8 +451,6 @@ struct MistralPacker } for (int bit = 0; bit < dbits; bit++) { for (int offset : offsets) { - log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))), - ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset)))); ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back( ctx->id(stringf("DATAAIN[%d]", bit + offset))); } |