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| author | gatecat <gatecat@ds0.me> | 2021-08-26 14:58:43 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-08-26 14:58:43 +0100 |
| commit | 0e83db47a067b55f45567c89a08af470196a18e7 (patch) | |
| tree | d9863bfeb37782dfb405e274077f627e854973b0 /mistral | |
| parent | 7f8e467acdb0d3803823802053691e6f73755e20 (diff) | |
| download | nextpnr-0e83db47a067b55f45567c89a08af470196a18e7.tar.gz nextpnr-0e83db47a067b55f45567c89a08af470196a18e7.tar.bz2 nextpnr-0e83db47a067b55f45567c89a08af470196a18e7.zip | |
clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral')
| -rw-r--r-- | mistral/bitstream.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 665005e9..f0e9c003 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -329,9 +329,9 @@ struct MistralBitgen } for (int i = 0; i < 3; i++) { // Check for fabric->clock routing - if (ctx->wires_connected(ctx->get_port(block_type, CycloneV::pos2x(pos), CycloneV::pos2y(pos), -1, - CycloneV::DATAIN, 0), - lab_data.clk_wires[i])) + if (ctx->wires_connected( + ctx->get_port(block_type, CycloneV::pos2x(pos), CycloneV::pos2y(pos), -1, CycloneV::DATAIN, 0), + lab_data.clk_wires[i])) cv->bmux_m_set(block_type, pos, CycloneV::CLKA_SEL, 0, CycloneV::GIN2); } } |