diff options
| author | gatecat <gatecat@ds0.me> | 2021-05-15 10:26:27 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 14:54:33 +0100 |
| commit | 9221acc9e211766d79d7c7dde5d5fc8bb053354d (patch) | |
| tree | 406159fd26ce543165b729cb441c486195d707d6 /mistral/lab.cc | |
| parent | 4d32c4f2fcb5c5e5ca21100f4473acb2c4cda3b0 (diff) | |
| download | nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.tar.gz nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.tar.bz2 nextpnr-9221acc9e211766d79d7c7dde5d5fc8bb053354d.zip | |
mistral: Fix ENA and ACLR bitstream generation
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral/lab.cc')
| -rw-r--r-- | mistral/lab.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/mistral/lab.cc b/mistral/lab.cc index 838c72a3..d34cc0ca 100644 --- a/mistral/lab.cc +++ b/mistral/lab.cc @@ -616,6 +616,11 @@ void Arch::assign_control_sets(uint32_t lab) bool legal = worker.run(this, lab); NPNR_ASSERT(legal); auto &lab_data = labs.at(lab); + + for (int j = 0; j < 2; j++) { + lab_data.aclr_used[j] = false; + } + for (uint8_t alm = 0; alm < 10; alm++) { auto &alm_data = lab_data.alms.at(alm); for (uint8_t i = 0; i < 4; i++) { @@ -648,6 +653,7 @@ void Arch::assign_control_sets(uint32_t lab) log_info("Assigned ACLR set %d to FF %s (%s)\n", i, nameOf(ff), getCtx()->nameOfBel(ff_bel)); } reserve_route(lab_data.aclr_wires[j], aclr_wire); + lab_data.aclr_used[j] = (aclr_sig.net != nullptr); alm_data.aclr_idx[i / 2] = j; break; } |