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authorOlivier Galibert <galibert@pobox.com>2022-01-18 22:37:35 +0100
committerOlivier Galibert <galibert@pobox.com>2022-01-18 22:37:35 +0100
commit91a0eb93672e9c764f03fd1b0a7d22595a61c516 (patch)
tree474661f20ac357b1491b8278e1824850027600a1 /mistral/io.cc
parentb5fc788153bd011a4476946af5ccebde05fd2ad2 (diff)
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Mistral: fix gpio OE, add hmc bypass support
Diffstat (limited to 'mistral/io.cc')
-rw-r--r--mistral/io.cc10
1 files changed, 6 insertions, 4 deletions
diff --git a/mistral/io.cc b/mistral/io.cc
index dab3672e..a0a01af3 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -30,10 +30,12 @@ void Arch::create_gpio(int x, int y)
WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
- // FIXME: is the port index of zero always correct?
- add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
- add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
- add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+ if(has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
+ // FIXME: is the port index of zero always correct?
+ add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
+ add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
+ add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+ }
bel_data(bel).block_index = z;
}
}