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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-02-04 09:03:36 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2022-02-04 09:03:36 +1000 |
| commit | eb5d3b3197b18b9bc3990dac85faee63f17f3f16 (patch) | |
| tree | 71bb36fd895b888c1a01ea044b3ad4587d07ce9d /mistral/bitstream.cc | |
| parent | 604260a0d7344627cea82198512384319c705105 (diff) | |
| parent | 5007cd3603d71f10924bb97acfe42d50d2ebcbd4 (diff) | |
| download | nextpnr-eb5d3b3197b18b9bc3990dac85faee63f17f3f16.tar.gz nextpnr-eb5d3b3197b18b9bc3990dac85faee63f17f3f16.tar.bz2 nextpnr-eb5d3b3197b18b9bc3990dac85faee63f17f3f16.zip | |
Merge branch 'master' into diff-locations
Diffstat (limited to 'mistral/bitstream.cc')
| -rw-r--r-- | mistral/bitstream.cc | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 340f4b96..e18d1413 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -39,14 +39,14 @@ struct MistralBitgen { auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi); auto rn1 = cv->pnode_to_rnode(pn1); - if(rn1) + if (rn1) return rn1; - if(bt == CycloneV::GPIO) { + if (bt == CycloneV::GPIO) { auto pn2 = cv->p2p_to(pn1); - if(!pn2) { + if (!pn2) { auto pnv = cv->p2p_from(pn1); - if(!pnv.empty()) + if (!pnv.empty()) pn2 = pnv[0]; } auto pn3 = cv->hmc_get_bypass(pn2); @@ -97,9 +97,11 @@ struct MistralBitgen // Output gpios must also bypass things in the associated dqs auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1)); - if(dqs) { - cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA); - cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f); + if (dqs) { + cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), + CycloneV::SEL_LOCKED_DPA); + cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, + CycloneV::pn2bi(dqs), 0x1f); } } // There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to |