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| author | gatecat <gatecat@ds0.me> | 2022-03-18 19:44:35 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-18 19:44:35 +0000 |
| commit | 7703cf61d0170ec3ac9db9a66cc99cbf5a8bbcf3 (patch) | |
| tree | 6e6fc91202e567f85e324ff4b6398aa505d170a7 /mistral/bitstream.cc | |
| parent | 051228c49a6c25a861c9ef7bcbadd52d0e0c7060 (diff) | |
| parent | 5e9236f9d4679d4596f0e593cdeff674229f5818 (diff) | |
| download | nextpnr-7703cf61d0170ec3ac9db9a66cc99cbf5a8bbcf3.tar.gz nextpnr-7703cf61d0170ec3ac9db9a66cc99cbf5a8bbcf3.tar.bz2 nextpnr-7703cf61d0170ec3ac9db9a66cc99cbf5a8bbcf3.zip | |
Merge pull request #955 from YosysHQ/gatecat/mistral-updates-2
mistral: Updated CLK mux select name
Diffstat (limited to 'mistral/bitstream.cc')
| -rw-r--r-- | mistral/bitstream.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 80490f1f..3e1b8b66 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -114,7 +114,7 @@ struct MistralBitgen { (void)ci; // currently unused auto pos = CycloneV::xy2pos(x, y); - cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing + cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SEL, bi, 0x1b); // hardcode to general routing cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB); } |