diff options
| author | Lofty <dan.ravensloft@gmail.com> | 2022-03-07 18:22:56 +0000 |
|---|---|---|
| committer | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 17:13:54 +0000 |
| commit | 3e688a3ac9ae35a894d5c2c19f2d9591b746d8da (patch) | |
| tree | a5b8fe410100bcc87712b076001ff72da5fd4ad0 /mistral/bitstream.cc | |
| parent | 9be65cd67c6a40ddc35460b97a014bbcd0af2f85 (diff) | |
| download | nextpnr-3e688a3ac9ae35a894d5c2c19f2d9591b746d8da.tar.gz nextpnr-3e688a3ac9ae35a894d5c2c19f2d9591b746d8da.tar.bz2 nextpnr-3e688a3ac9ae35a894d5c2c19f2d9591b746d8da.zip | |
mistral: fixes and debug info
Diffstat (limited to 'mistral/bitstream.cc')
| -rw-r--r-- | mistral/bitstream.cc | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 660e3671..6a2c3825 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -118,7 +118,7 @@ struct MistralBitgen cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB); } - void write_m10k_cell(CellInfo* ci, int x, int y, int bi) + void write_m10k_cell(CellInfo *ci, int x, int y, int bi) { auto pos = CycloneV::xy2pos(x, y); @@ -128,31 +128,32 @@ struct MistralBitgen cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1); cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64()); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST); - cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG); + cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::ASYNC); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SAEN_DELAY, bi, 2); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WL_DELAY, bi, 2); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1); + cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1); cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64()); cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST); - cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG); + cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::ASYNC); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SAEN_DELAY, bi, 2); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WL_DELAY, bi, 2); cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_WR_TIMER_PULSE, bi, 0x0b); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1); - cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1); + cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_CLK_SEL, bi, 1); + cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TOP_W_INV, bi, 1); + cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::TOP_W_SEL, bi, 1); + cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::BOT_CLK_INV, bi, 1); + cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::BOT_W_SEL, bi, 1); - cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 1); + cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::TRUE_DUAL_PORT, bi, 0); cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::DISABLE_UNUSED, bi, 0); + // Note for future us: the RAM init contents are inverted. for (int bi = 0; bi < 256; bi++) cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::RAM, bi, 0xffffffffff); } |