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| author | gatecat <gatecat@ds0.me> | 2021-10-05 13:59:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-05 13:59:36 +0100 |
| commit | 4f17a1711abc6d74c367457a1956c779a789e0e9 (patch) | |
| tree | d8a2c6f41f7c97b3ba56d73821a4d462ccce3842 /mistral/archdefs.h | |
| parent | 9c32e2d852ef4030cf7ee74331e09e32a4d21f9a (diff) | |
| parent | f5f7ef68649e873e6e5dc912544ed8abb5eb8fc3 (diff) | |
| download | nextpnr-4f17a1711abc6d74c367457a1956c779a789e0e9.tar.gz nextpnr-4f17a1711abc6d74c367457a1956c779a789e0e9.tar.bz2 nextpnr-4f17a1711abc6d74c367457a1956c779a789e0e9.zip | |
Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2
mistral: Adding support for MLABs as memory
Diffstat (limited to 'mistral/archdefs.h')
| -rw-r--r-- | mistral/archdefs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/mistral/archdefs.h b/mistral/archdefs.h index 8b4256ab..f4040398 100644 --- a/mistral/archdefs.h +++ b/mistral/archdefs.h @@ -195,6 +195,11 @@ struct ArchCellInfo : BaseClusterInfo bool is_carry, is_shared, is_extended; bool carry_start, carry_end; + + // MLABs with compatible write ports have this set to the same non-negative integer. -1 means this isn't a + // MLAB + int mlab_group; + ControlSig wclk, we; } combInfo; struct { |