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author | gatecat <gatecat@ds0.me> | 2021-02-11 11:10:32 +0000 |
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committer | gatecat <gatecat@ds0.me> | 2021-02-12 10:36:59 +0000 |
commit | 510969ab9704865f87c7c0bd09e0185b729feffc (patch) | |
tree | 39a6e35998d92f5066f21f8055a17fb7a7428f98 /machxo2/synth/synth_machxo2.tcl | |
parent | c956cae8244c094783edc7101fd0ca542c24e55b (diff) | |
download | nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.tar.gz nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.tar.bz2 nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.zip |
Create machxo2 backend (renamed from generic).
Signed-off-by: William D. Jones <thor0505@comcast.net>
Diffstat (limited to 'machxo2/synth/synth_machxo2.tcl')
-rw-r--r-- | machxo2/synth/synth_machxo2.tcl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/machxo2/synth/synth_machxo2.tcl b/machxo2/synth/synth_machxo2.tcl new file mode 100644 index 00000000..e5d88e0d --- /dev/null +++ b/machxo2/synth/synth_machxo2.tcl @@ -0,0 +1,24 @@ +# Usage +# tcl synth_generic.tcl {K} {out.json} + +set LUT_K 4 +if {$argc > 0} { set LUT_K [lindex $argv 0] } +yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v +yosys hierarchy -check +yosys proc +yosys flatten +yosys tribuf -logic +yosys deminout +yosys synth -run coarse +yosys memory_map +yosys opt -full +yosys techmap -map +/techmap.v +yosys opt -fast +yosys abc -lut $LUT_K -dress +yosys clean +yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v +yosys clean +yosys hierarchy -check +yosys stat + +if {$argc > 1} { yosys write_json [lindex $argv 1] } |