diff options
| author | William D. Jones <thor0505@comcast.net> | 2020-12-07 02:15:29 -0500 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-02-12 10:36:59 +0000 |
| commit | 8a94a3451f88ca6632991ef3f2a61e4ed9a4ac5b (patch) | |
| tree | ef4bb9d245d4639b5cbffdca7dd5a3554984aa88 /machxo2/arch.cc | |
| parent | 5f748272fc118f5fdf8b5389188434c6070ca917 (diff) | |
| download | nextpnr-8a94a3451f88ca6632991ef3f2a61e4ed9a4ac5b.tar.gz nextpnr-8a94a3451f88ca6632991ef3f2a61e4ed9a4ac5b.tar.bz2 nextpnr-8a94a3451f88ca6632991ef3f2a61e4ed9a4ac5b.zip | |
machxo2: Stub valid BEL functions with comment. Place phase segfaults.
Diffstat (limited to 'machxo2/arch.cc')
| -rw-r--r-- | machxo2/arch.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 42d93f16..d9753528 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -382,12 +382,17 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { - return false; + // FIXME: Unlike ECP5, SLICEs in a given tile do not share a clock, so + // any SLICE Cell is valid for any BEL, even if some cells are already + // bound to BELs in the tile. However, this may need to be filled in once + // more than one LUT4 and DFF type is supported. + return true; } bool Arch::isBelLocationValid(BelId bel) const { - return false; + // FIXME: Same deal as isValidBelForCell. + return true; } #ifdef WITH_HEAP |