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author | David Shah <davey1576@gmail.com> | 2019-03-25 16:24:02 +0000 |
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committer | GitHub <noreply@github.com> | 2019-03-25 16:24:02 +0000 |
commit | c67b8259bb8b31ba3f6aa30c431fef222e5f2f65 (patch) | |
tree | 6f427acacd9545150ad82465dda0e6c3d130c1e2 /ice40 | |
parent | 0d064c05f91b548638530e6e159ca9f8aa0fa352 (diff) | |
parent | 25e3350675c091c2fb54e51c9fcb7e79bbe6e279 (diff) | |
download | nextpnr-c67b8259bb8b31ba3f6aa30c431fef222e5f2f65.tar.gz nextpnr-c67b8259bb8b31ba3f6aa30c431fef222e5f2f65.tar.bz2 nextpnr-c67b8259bb8b31ba3f6aa30c431fef222e5f2f65.zip |
Merge pull request #219 from daveshah1/placer_heap
HeAP-based analytical placer
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/arch.cc | 24 | ||||
-rw-r--r-- | ice40/arch.h | 3 | ||||
-rw-r--r-- | ice40/arch_pybindings.cc | 7 | ||||
-rw-r--r-- | ice40/examples/blinky/blinky.pcf (renamed from ice40/blinky.pcf) | 0 | ||||
-rw-r--r-- | ice40/examples/blinky/blinky.proj (renamed from ice40/blinky.proj) | 0 | ||||
-rwxr-xr-x | ice40/examples/blinky/blinky.sh (renamed from ice40/blinky.sh) | 0 | ||||
-rw-r--r-- | ice40/examples/blinky/blinky.v (renamed from ice40/blinky.v) | 0 | ||||
-rw-r--r-- | ice40/examples/blinky/blinky.ys (renamed from ice40/blinky.ys) | 0 | ||||
-rw-r--r-- | ice40/examples/blinky/blinky_tb.v (renamed from ice40/blinky_tb.v) | 0 | ||||
-rw-r--r-- | ice40/examples/floorplan/.gitignore | 4 | ||||
-rw-r--r-- | ice40/examples/floorplan/floorplan.py | 5 | ||||
-rwxr-xr-x | ice40/examples/floorplan/floorplan.sh | 6 | ||||
-rw-r--r-- | ice40/examples/floorplan/floorplan.v | 22 | ||||
-rw-r--r-- | ice40/examples/floorplan/icebreaker.pcf | 5 | ||||
-rw-r--r-- | ice40/main.cc | 1 |
15 files changed, 73 insertions, 4 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index fbe882fc..b0839fa5 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -26,10 +26,10 @@ #include "log.h" #include "nextpnr.h" #include "placer1.h" +#include "placer_heap.h" #include "router1.h" #include "timing_opt.h" #include "util.h" - NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- @@ -671,8 +671,18 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay bool Arch::place() { - if (!placer1(getCtx(), Placer1Cfg(getCtx()))) - return false; + std::string placer = str_or_default(settings, id("placer"), defaultPlacer); + if (placer == "heap") { + PlacerHeapCfg cfg(getCtx()); + cfg.ioBufTypes.insert(id_SB_IO); + if (!placer_heap(getCtx(), cfg)) + return false; + } else if (placer == "sa") { + if (!placer1(getCtx(), Placer1Cfg(getCtx()))) + return false; + } else { + log_error("iCE40 architecture does not support placer '%s'\n", placer.c_str()); + } if (bool_or_default(settings, id("opt_timing"), false)) { TimingOptCfg tocfg(getCtx()); tocfg.cellTypes.insert(id_ICESTORM_LC); @@ -1198,4 +1208,12 @@ void Arch::assignCellInfo(CellInfo *cell) } } +const std::string Arch::defaultPlacer = "sa"; + +const std::vector<std::string> Arch::availablePlacers = {"sa", +#ifdef WITH_HEAP + "heap" +#endif +}; + NEXTPNR_NAMESPACE_END diff --git a/ice40/arch.h b/ice40/arch.h index 706043b2..ea29f4f1 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -897,6 +897,9 @@ struct Arch : BaseCtx IdString glb_net = getWireName(getBelPinWire(bel, id_GLOBAL_BUFFER_OUTPUT)); return std::stoi(std::string("") + glb_net.str(this).back()); } + + static const std::string defaultPlacer; + static const std::vector<std::string> availablePlacers; }; void ice40DelayFuzzerMain(Context *ctx); diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index f0ca584b..bc0bfb84 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -144,6 +144,13 @@ void arch_wrap_python() fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>, pass_through<float>>::def_wrap(ctx_cls, "addClock"); + fn_wrapper_5a_v<Context, decltype(&Context::createRectangularRegion), &Context::createRectangularRegion, + conv_from_str<IdString>, pass_through<int>, pass_through<int>, pass_through<int>, + pass_through<int>>::def_wrap(ctx_cls, "createRectangularRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::addBelToRegion), &Context::addBelToRegion, conv_from_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "addBelToRegion"); + fn_wrapper_2a_v<Context, decltype(&Context::constrainCellToRegion), &Context::constrainCellToRegion, + conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "constrainCellToRegion"); WRAP_RANGE(Bel, conv_to_str<BelId>); WRAP_RANGE(Wire, conv_to_str<WireId>); diff --git a/ice40/blinky.pcf b/ice40/examples/blinky/blinky.pcf index 141dfcc8..141dfcc8 100644 --- a/ice40/blinky.pcf +++ b/ice40/examples/blinky/blinky.pcf diff --git a/ice40/blinky.proj b/ice40/examples/blinky/blinky.proj index f5bb9f88..f5bb9f88 100644 --- a/ice40/blinky.proj +++ b/ice40/examples/blinky/blinky.proj diff --git a/ice40/blinky.sh b/ice40/examples/blinky/blinky.sh index a2326fc3..a2326fc3 100755 --- a/ice40/blinky.sh +++ b/ice40/examples/blinky/blinky.sh diff --git a/ice40/blinky.v b/ice40/examples/blinky/blinky.v index 36eaee86..36eaee86 100644 --- a/ice40/blinky.v +++ b/ice40/examples/blinky/blinky.v diff --git a/ice40/blinky.ys b/ice40/examples/blinky/blinky.ys index a5dd2c85..a5dd2c85 100644 --- a/ice40/blinky.ys +++ b/ice40/examples/blinky/blinky.ys diff --git a/ice40/blinky_tb.v b/ice40/examples/blinky/blinky_tb.v index f80b5e64..f80b5e64 100644 --- a/ice40/blinky_tb.v +++ b/ice40/examples/blinky/blinky_tb.v diff --git a/ice40/examples/floorplan/.gitignore b/ice40/examples/floorplan/.gitignore new file mode 100644 index 00000000..d93659be --- /dev/null +++ b/ice40/examples/floorplan/.gitignore @@ -0,0 +1,4 @@ +*.json +*.asc +*.bin +__pycache__
\ No newline at end of file diff --git a/ice40/examples/floorplan/floorplan.py b/ice40/examples/floorplan/floorplan.py new file mode 100644 index 00000000..85c53ccd --- /dev/null +++ b/ice40/examples/floorplan/floorplan.py @@ -0,0 +1,5 @@ +ctx.createRectangularRegion("osc", 1, 1, 1, 4) +for cell, cellinfo in ctx.cells: + if "ringosc" in cellinfo.attrs: + print("Floorplanned cell %s" % cell) + ctx.constrainCellToRegion(cell, "osc") diff --git a/ice40/examples/floorplan/floorplan.sh b/ice40/examples/floorplan/floorplan.sh new file mode 100755 index 00000000..e0ed7a64 --- /dev/null +++ b/ice40/examples/floorplan/floorplan.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash +set -ex +yosys -p "synth_ice40 -top top -json floorplan.json" floorplan.v +../../../nextpnr-ice40 --up5k --json floorplan.json --pcf icebreaker.pcf --asc floorplan.asc --ignore-loops --pre-place floorplan.py +icepack floorplan.asc floorplan.bin +iceprog floorplan.bin diff --git a/ice40/examples/floorplan/floorplan.v b/ice40/examples/floorplan/floorplan.v new file mode 100644 index 00000000..8f99ed4e --- /dev/null +++ b/ice40/examples/floorplan/floorplan.v @@ -0,0 +1,22 @@ +module top(output LED1, LED2, LED3, LED4, LED5); + localparam N = 31; + wire [N:0] x; + assign x[0] = x[N]; + + genvar ii; + generate + + for (ii = 0; ii < N; ii = ii + 1) begin + (* ringosc *) + SB_LUT4 #(.LUT_INIT(1)) lut_i(.I0(x[ii]), .I1(), .I2(), .I3(), .O(x[ii+1])); + end + endgenerate + + assign clk = x[N]; + + + reg [19:0] ctr; + always @(posedge clk) + ctr <= ctr + 1'b1; + assign {LED5, LED4, LED3, LED2, LED1} = ctr[19:15]; +endmodule diff --git a/ice40/examples/floorplan/icebreaker.pcf b/ice40/examples/floorplan/icebreaker.pcf new file mode 100644 index 00000000..ac7ebf9e --- /dev/null +++ b/ice40/examples/floorplan/icebreaker.pcf @@ -0,0 +1,5 @@ +set_io -nowarn LED1 26 +set_io -nowarn LED2 27 +set_io -nowarn LED3 25 +set_io -nowarn LED4 23 +set_io -nowarn LED5 21 diff --git a/ice40/main.cc b/ice40/main.cc index 2313c2ae..9b79a08c 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -176,7 +176,6 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext() ctx->settings[ctx->id("opt_timing")] = "1"; if (vm.count("pcf-allow-unconstrained")) ctx->settings[ctx->id("pcf_allow_unconstrained")] = "1"; - return ctx; } |