Merge branch 'master' into q3k/treemodel-fast

7 files changed, 262 insertions, 65 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 3803f842..fd68e972 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -141,18 +141,23 @@ Arch::Arch(ArchArgs args) : args(args)
 
 #ifdef ICE40_HX1K_ONLY
     if (args.type == ArchArgs::HX1K) {
+        fast_part = true;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
     } else {
         log_error("Unsupported iCE40 chip type.\n");
     }
 #else
     if (args.type == ArchArgs::LP384) {
+        fast_part = false;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
     } else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
+        fast_part = args.type == ArchArgs::HX1K;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
     } else if (args.type == ArchArgs::UP5K) {
+        fast_part = false;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
     } else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
+        fast_part = args.type == ArchArgs::HX8K;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
     } else {
         log_error("Unsupported iCE40 chip type.\n");
@@ -306,9 +311,23 @@ PortType Arch::getBelPinType(BelId bel, PortPin pin) const
     int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
     const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
 
-    for (int i = 0; i < num_bel_wires; i++)
-        if (bel_wires[i].port == pin)
-            return PortType(bel_wires[i].type);
+    if (num_bel_wires < 7) {
+        for (int i = 0; i < num_bel_wires; i++) {
+            if (bel_wires[i].port == pin)
+                return PortType(bel_wires[i].type);
+        }
+    } else {
+        int b = 0, e = num_bel_wires-1;
+        while (b <= e) {
+            int i = (b+e) / 2;
+            if (bel_wires[i].port == pin)
+                return PortType(bel_wires[i].type);
+            if (bel_wires[i].port > pin)
+                e = i-1;
+            else
+                b = i+1;
+        }
+    }
 
     return PORT_INOUT;
 }
@@ -322,10 +341,25 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
     int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
     const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
 
-    for (int i = 0; i < num_bel_wires; i++) {
-        if (bel_wires[i].port == pin) {
-            ret.index = bel_wires[i].wire_index;
-            break;
+    if (num_bel_wires < 7) {
+        for (int i = 0; i < num_bel_wires; i++) {
+            if (bel_wires[i].port == pin) {
+                ret.index = bel_wires[i].wire_index;
+                break;
+            }
+        }
+    } else {
+        int b = 0, e = num_bel_wires-1;
+        while (b <= e) {
+            int i = (b+e) / 2;
+            if (bel_wires[i].port == pin) {
+                ret.index = bel_wires[i].wire_index;
+                break;
+            }
+            if (bel_wires[i].port > pin)
+                e = i-1;
+            else
+                b = i+1;
         }
     }
 
@@ -770,29 +804,29 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
 
 // -----------------------------------------------------------------------
 
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
 {
     if (cell->type == id_icestorm_lc) {
         if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
             (toPort == id_o || toPort == id_lo)) {
-            delay = 450;
+            delay.delay = 450;
             return true;
         } else if (fromPort == id_cin && toPort == id_cout) {
-            delay = 120;
+            delay.delay = 120;
             return true;
         } else if (fromPort == id_i1 && toPort == id_cout) {
-            delay = 260;
+            delay.delay = 260;
             return true;
         } else if (fromPort == id_i2 && toPort == id_cout) {
-            delay = 230;
+            delay.delay = 230;
             return true;
         } else if (fromPort == id_clk && toPort == id_o) {
-            delay = 540;
+            delay.delay = 540;
             return true;
         }
     } else if (cell->type == id_icestorm_ram) {
         if (fromPort == id_rclk) {
-            delay = 2140;
+            delay.delay = 2140;
             return true;
         }
     }
diff --git a/ice40/arch.h b/ice40/arch.h
index 51cbe725..1d68ec4a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -44,9 +44,9 @@ template <typename T> struct RelPtr
 };
 
 NPNR_PACKED_STRUCT(struct BelWirePOD {
-    int32_t wire_index;
     PortPin port;
     int32_t type;
+    int32_t wire_index;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
@@ -66,7 +66,8 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     // RelPtr<char> name;
     int32_t src, dst;
-    int32_t delay;
+    int32_t fast_delay;
+    int32_t slow_delay;
     int8_t x, y;
     int16_t src_seg, dst_seg;
     int16_t switch_mask;
@@ -89,6 +90,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     int32_t num_segments;
     RelPtr<WireSegmentPOD> segments;
 
+    int32_t fast_delay;
+    int32_t slow_delay;
+
     int8_t x, y;
     WireType type;
     int8_t padding_0;
@@ -344,6 +348,7 @@ struct ArchArgs
 
 struct Arch : BaseCtx
 {
+    bool fast_part;
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info;
 
@@ -524,6 +529,11 @@ struct Arch : BaseCtx
     DelayInfo getWireDelay(WireId wire) const
     {
         DelayInfo delay;
+        NPNR_ASSERT(wire != WireId());
+        if (fast_part)
+            delay.delay =  chip_info->wire_data[wire.index].fast_delay;
+        else
+            delay.delay =  chip_info->wire_data[wire.index].slow_delay;
         return delay;
     }
 
@@ -637,7 +647,10 @@ struct Arch : BaseCtx
     {
         DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
-        delay.delay = chip_info->pip_data[pip.index].delay;
+        if (fast_part)
+            delay.delay = chip_info->pip_data[pip.index].fast_delay;
+        else
+            delay.delay = chip_info->pip_data[pip.index].slow_delay;
         return delay;
     }
 
@@ -709,7 +722,7 @@ struct Arch : BaseCtx
 
     // Get the delay through a cell from one port to another, returning false
     // if no path exists
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
     // Get the associated clock to a port, or empty if the port is combinational
     IdString getPortClock(const CellInfo *cell, IdString port) const;
     // Return true if a port is a clock
diff --git a/ice40/benchmark/Makefile b/ice40/benchmark/Makefile
index 5e16d9b0..5a276b18 100644
--- a/ice40/benchmark/Makefile
+++ b/ice40/benchmark/Makefile
@@ -1,3 +1,5 @@
+SHELL = /bin/bash
+
 reports::
 
 define mkreport
@@ -10,10 +12,10 @@ report_n$1.txt: hx8kdemo_n$1.asc
 	icetime -m -r report_n$1.txt -d hx8k hx8kdemo_n$1.asc
 
 hx8kdemo_a$1.asc: hx8kdemo.blif
-	arachne-pnr -d 8k -p hx8kdemo.pcf -o hx8kdemo_a$1.asc -s 1$1 hx8kdemo.blif > hx8kdemo_a$1.log 2>&1
+	{ time arachne-pnr -d 8k -p hx8kdemo.pcf -o hx8kdemo_a$1.asc -s 1$1 hx8kdemo.blif; } > hx8kdemo_a$1.log 2>&1
 
 hx8kdemo_n$1.asc: hx8kdemo.json
-	../../nextpnr-ice40 --asc hx8kdemo_n$1.asc --json hx8kdemo.json --pcf hx8kdemo.pcf --hx8k --seed 1$1 > hx8kdemo_n$1.log 2>&1
+	{ time ../../nextpnr-ice40 --asc hx8kdemo_n$1.asc --json hx8kdemo.json --pcf hx8kdemo.pcf --hx8k --seed 1$1; } > hx8kdemo_n$1.log 2>&1
 endef
 
 $(foreach i,0 1 2 3 4 5 6 7 8 9,$(eval $(call mkreport,$(i))))
diff --git a/ice40/benchmark/report.ipynb b/ice40/benchmark/report.ipynb
index 3232f38c..b4e03283 100644
--- a/ice40/benchmark/report.ipynb
+++ b/ice40/benchmark/report.ipynb
@@ -11,36 +11,58 @@
     "%matplotlib inline\n",
     "import numpy as np\n",
     "import matplotlib.pyplot as plt\n",
-    "import subprocess\n",
+    "import subprocess, re\n",
     "\n",
     "gitrev = subprocess.getoutput(\"git rev-parse --short HEAD\")\n",
     "\n",
-    "data_a = 1 + np.zeros(10)\n",
-    "data_n = 1 + np.zeros(10)\n",
+    "data_a = np.zeros((10, 2))\n",
+    "data_n = np.zeros((10, 2))\n",
     "\n",
     "for i in range(10):\n",
     "    try:\n",
     "        with open(\"report_a%d.txt\" % i, \"r\") as f:\n",
     "            for line in f:\n",
     "                if line.startswith(\"Total path delay:\"):\n",
-    "                    data_a[i] = float(line.split()[3])\n",
+    "                    data_a[i, 0] = float(line.split()[3])\n",
     "    except:\n",
-    "        pass\n",
+    "        data_a[i, 0] = 1.0\n",
+    "    \n",
     "    try:\n",
     "        with open(\"report_n%d.txt\" % i, \"r\") as f:\n",
     "            for line in f:\n",
     "                if line.startswith(\"Total path delay:\"):\n",
-    "                    data_n[i] = float(line.split()[3])\n",
+    "                    data_n[i, 0] = float(line.split()[3])\n",
     "    except:\n",
-    "        pass\n",
+    "        data_n[i, 0] = 1.0\n",
+    "    \n",
+    "    with open(\"hx8kdemo_a%d.log\" % i, \"r\") as f:\n",
+    "        for line in f:\n",
+    "            match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n",
+    "            if match:\n",
+    "                data_a[i, 1] = float(match.group(1)) + float(match.group(2))/60\n",
+    "    \n",
+    "    with open(\"hx8kdemo_n%d.log\" % i, \"r\") as f:\n",
+    "        for line in f:\n",
+    "            match = re.match(r\"real\\s+(\\d+)m(\\d+)\", line)\n",
+    "            if match:\n",
+    "                data_n[i, 1] = float(match.group(1)) + float(match.group(2))/60\n",
     "\n",
     "plt.figure(figsize=(9,3))\n",
     "plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n",
-    "plt.bar(np.arange(10), data_a, color='blue')\n",
-    "plt.bar(15+np.arange(10), data_n, color='red')\n",
+    "plt.bar(np.arange(10), data_a[:, 0], color='blue')\n",
+    "plt.bar(15+np.arange(10), data_n[:, 0], color='red')\n",
     "plt.ylabel('Longest path (ns)')\n",
     "plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n",
     "plt.xlim(-2, 27)\n",
+    "plt.show()\n",
+    "\n",
+    "plt.figure(figsize=(9,3))\n",
+    "plt.title(\"nextpnr -- ice40/benchmark/ -- %s\" % gitrev)\n",
+    "plt.bar(np.arange(10), data_a[:, 1], color='blue')\n",
+    "plt.bar(15+np.arange(10), data_n[:, 1], color='red')\n",
+    "plt.ylabel('Runtime (minutes)')\n",
+    "plt.xticks([5, 20], [\"arachne-pnr\", \"nextpnr\"])\n",
+    "plt.xlim(-2, 27)\n",
     "plt.show()"
    ]
   }
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index b6af8fcf..97ccbe48 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -9,6 +9,8 @@ parser = argparse.ArgumentParser(description="convert ICE40 chip database")
 parser.add_argument("filename", type=str, help="chipdb input filename")
 parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc")
 parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
+parser.add_argument("--fast", type=str, help="path to timing data for fast part")
+parser.add_argument("--slow", type=str, help="path to timing data for slow part")
 args = parser.parse_args()
 
 dev_name = None
@@ -51,6 +53,9 @@ wiretypes = dict()
 gfx_wire_ids = dict()
 wire_segments = dict()
 
+fast_timings = None
+slow_timings = None
+
 with open(args.portspins) as f:
     for line in f:
         line = line.replace("(", " ")
@@ -77,6 +82,31 @@ with open(args.gfxh) as f:
             name = line.strip().rstrip(",")
             gfx_wire_ids[name] = idx
 
+def read_timings(filename):
+    db = dict()
+    with open(filename) as f:
+        cell = None
+        for line in f:
+            line = line.split()
+            if len(line) == 0:
+                continue
+            if line[0] == "CELL":
+                cell = line[1]
+            if line[0] == "IOPATH":
+                key = "%s.%s.%s" % (cell, line[1], line[2])
+                v1 = line[3].split(":")[2]
+                v2 = line[4].split(":")[2]
+                v1 = 0 if v1 == "*" else float(v1)
+                v2 = 0 if v2 == "*" else float(v2)
+                db[key] = max(v1, v2)
+    return db
+
+if args.fast is not None:
+    fast_timings = read_timings(args.fast)
+
+if args.slow is not None:
+    slow_timings = read_timings(args.slow)
+
 beltypes["ICESTORM_LC"] = 1
 beltypes["ICESTORM_RAM"] = 2
 beltypes["SB_IO"] = 3
@@ -184,46 +214,75 @@ def wire_type(name):
         assert 0
     return wt
 
-def pipdelay(src, dst):
-    src = wire_names_r[src]
-    dst = wire_names_r[dst]
+def pipdelay(src_idx, dst_idx, db):
+    if db is None:
+        return 0
+
+    src = wire_names_r[src_idx]
+    dst = wire_names_r[dst_idx]
     src_type = wire_type(src[2])
     dst_type = wire_type(dst[2])
 
-    if src_type == "LOCAL" and dst_type == "LOCAL":
-       return 250
+    if dst[2].startswith("sp4_") or dst[2].startswith("span4_"):
+        if src[2].startswith("sp12_") or src[2].startswith("span12_"):
+            return db["Sp12to4.I.O"]
+
+        if src[2].startswith("span4_"):
+            return db["IoSpan4Mux.I.O"]
+
+        if dst[2].startswith("sp4_h_"):
+            return db["Span4Mux_h4.I.O"]
+        else:
+            return db["Span4Mux_v4.I.O"]
+
+    if dst[2].startswith("sp12_") or dst[2].startswith("span12_"):
+        if dst[2].startswith("sp12_h_"):
+            return db["Span12Mux_h12.I.O"]
+        else:
+            return db["Span12Mux_v12.I.O"]
 
-    if src_type == "GLOBAL" and dst_type == "LOCAL":
-       return 400
+    if dst[2] in ("fabout", "clk"):
+        return 0 # FIXME?
 
-    # Local -> Span
+    if src[2].startswith("glb_netwk_") and dst[2].startswith("glb2local_"):
+        return 0 # FIXME?
 
-    if src_type == "LOCAL" and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 350
+    if dst[2] == "carry_in_mux":
+        return db["ICE_CARRY_IN_MUX.carryinitin.carryinitout"]
 
-    if src_type == "LOCAL" and dst_type in ("SP12_HORZ", "SP12_VERT"):
-       return 500
+    if dst[2] in ("lutff_global/clk", "io_global/inclk", "io_global/outclk", "ram/RCLK", "ram/WCLK"):
+        return db["ClkMux.I.O"]
 
-    # Span -> Local
+    if dst[2] in ("lutff_global/s_r", "io_global/latch", "ram/RE", "ram/WE"):
+        return db["SRMux.I.O"]
 
-    if src_type in ("SP4_HORZ", "SP4_VERT", "SP12_HORZ", "SP12_VERT") and dst_type == "LOCAL":
-       return 300
+    if dst[2] in ("lutff_global/cen", "io_global/cen", "ram/RCLKE", "ram/WCLKE"):
+        return db["CEMux.I.O"]
 
-    # Span -> Span
+    if dst[2].startswith("local_"):
+        return db["LocalMux.I.O"]
 
-    if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP12_HORZ", "SP12_VERT"):
-       return 450
+    if src[2].startswith("local_") and dst[2] in ("io_0/D_OUT_0", "io_0/D_OUT_1", "io_0/OUT_ENB", "io_1/D_OUT_0", "io_1/D_OUT_1", "io_1/OUT_ENB"):
+        return db["IoInMux.I.O"]
 
-    if src_type in ("SP4_HORZ", "SP4_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 300
+    if re.match(r"lutff_\d+/in_\d+", dst[2]):
+        return db["InMux.I.O"]
 
-    if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 380
+    if re.match(r"ram/(MASK|RADDR|WADDR|WDATA)_", dst[2]):
+        return db["InMux.I.O"]
 
-    # print(src, dst, src_type, dst_type, file=sys.stderr)
+    print(src, dst, src_idx, dst_idx, src_type, dst_type, file=sys.stderr)
     assert 0
 
+def wiredelay(wire_idx, db):
+    if db is None:
+        return 0
 
+    wire = wire_names_r[wire_idx]
+    wtype = wire_type(wire[2])
+
+    # FIXME
+    return 0
 
 def init_tiletypes(device):
     global num_tile_types, tile_sizes, tile_bits
@@ -448,13 +507,13 @@ def add_bel_input(bel, wire, port):
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port, 0))
+    bel_wires[bel].append((portpins[port], 0, wire))
 
 def add_bel_output(bel, wire, port):
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port, 1))
+    bel_wires[bel].append((portpins[port], 1, wire))
 
 def add_bel_lc(x, y, z):
     bel = len(bel_name)
@@ -715,14 +774,12 @@ bba.post('NEXTPNR_NAMESPACE_END')
 bba.push("chipdb_blob_%s" % dev_name)
 bba.r("chip_info_%s" % dev_name, "chip_info")
 
-index = 0
 for bel in range(len(bel_name)):
     bba.l("bel_wires_%d" % bel, "BelWirePOD")
-    for i in range(len(bel_wires[bel])):
-        bba.u32(bel_wires[bel][i][0], "wire_index")
-        bba.u32(portpins[bel_wires[bel][i][1]], "port")
-        bba.u32(bel_wires[bel][i][2], "type")
-        index += 1
+    for data in sorted(bel_wires[bel]):
+        bba.u32(data[0], "port")
+        bba.u32(data[1], "type")
+        bba.u32(data[2], "wire_index")
 
 bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
 for bel in range(len(bel_name)):
@@ -748,7 +805,8 @@ for wire in range(num_wires):
                 pi = dict()
                 pi["src"] = src
                 pi["dst"] = wire
-                pi["delay"] = pipdelay(src, wire)
+                pi["fast_delay"] = pipdelay(src, wire, fast_timings)
+                pi["slow_delay"] = pipdelay(src, wire, slow_timings)
                 pi["x"] = pip_xy[(src, wire)][0]
                 pi["y"] = pip_xy[(src, wire)][1]
                 pi["switch_mask"] = pip_xy[(src, wire)][2]
@@ -772,7 +830,8 @@ for wire in range(num_wires):
                 pi = dict()
                 pi["src"] = wire
                 pi["dst"] = dst
-                pi["delay"] = pipdelay(wire, dst)
+                pi["fast_delay"] = pipdelay(wire, dst, fast_timings)
+                pi["slow_delay"] = pipdelay(wire, dst, slow_timings)
                 pi["x"] = pip_xy[(wire, dst)][0]
                 pi["y"] = pip_xy[(wire, dst)][1]
                 pi["switch_mask"] = pip_xy[(wire, dst)][2]
@@ -891,6 +950,9 @@ for wire, info in enumerate(wireinfo):
     else:
         bba.u32(0, "segments")
 
+    bba.u32(wiredelay(wire, fast_timings), "fast_delay")
+    bba.u32(wiredelay(wire, slow_timings), "slow_delay")
+
     bba.u8(info["x"], "x")
     bba.u8(info["y"], "y")
     bba.u8(wiretypes[wire_type(info["name"])], "type")
@@ -923,7 +985,8 @@ for info in pipinfo:
     # bba.s("X%d/Y%d/%s->%s" % (info["x"], info["y"], src_segname, dst_segname), "name")
     bba.u32(info["src"], "src")
     bba.u32(info["dst"], "dst")
-    bba.u32(info["delay"], "delay")
+    bba.u32(info["fast_delay"], "fast_delay")
+    bba.u32(info["slow_delay"], "slow_delay")
     bba.u8(info["x"], "x")
     bba.u8(info["y"], "y")
     bba.u16(src_seg, "src_seg")
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 75061f44..02d4b4d8 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -14,17 +14,28 @@ file(MAKE_DIRECTORY ice40/chipdbs/)
 add_library(ice40_chipdb OBJECT ice40/chipdbs/)
 target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
 target_include_directories(ice40_chipdb PRIVATE ${family}/)
+
 if (MSVC)
     target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc)
     set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
     foreach (dev ${devices})
+        if (dev EQUAL "5k")
+            set(OPT_FAST "")
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-up5k.txt)
+        elseif(dev EQUAL "384")
+            set(OPT_FAST "")
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp384.txt)
+        else()
+            set(OPT_FAST --fast ${ICEBOX_ROOT}/timings-hx${dev}.txt)
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings-lp${dev}.txt)
+        endif()
         set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
         set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
         set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin)
         set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
         set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
         add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
-                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
+                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
                 DEPENDS ${DEV_TXT_DB} ${DB_PY}
                 )
         add_custom_command(OUTPUT ${DEV_CC_DB}
@@ -40,13 +51,23 @@ if (MSVC)
 else()
     target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
     foreach (dev ${devices})
+        if (dev EQUAL "5k")
+            set(OPT_FAST "")
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
+        elseif(dev EQUAL "384")
+            set(OPT_FAST "")
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
+        else()
+            set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
+            set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
+        endif()
         set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
         set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
         set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc)
         set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
         set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
         add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
-                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
+                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
                 COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
                 DEPENDS ${DEV_TXT_DB} ${DB_PY}
         )
diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc
index 9fde179d..0d14fb35 100644
--- a/ice40/place_legaliser.cc
+++ b/ice40/place_legaliser.cc
@@ -114,17 +114,58 @@ class PlacementLegaliser
   public:
     PlacementLegaliser(Context *ctx) : ctx(ctx){};
 
+    void print_stats(const char *point)
+    {
+        float distance_sum = 0;
+        float max_distance = 0;
+        int moved_cells = 0;
+        int unplaced_cells = 0;
+        for (auto orig : originalPositions) {
+            if (ctx->cells.at(orig.first)->bel == BelId()) {
+                unplaced_cells++;
+                continue;
+            }
+            Loc newLoc = ctx->getBelLocation(ctx->cells.at(orig.first)->bel);
+            if (newLoc != orig.second) {
+                float distance = std::sqrt(std::pow(newLoc.x - orig.second.x, 2) + pow(newLoc.y - orig.second.y, 2));
+                moved_cells++;
+                distance_sum += distance;
+                if (distance > max_distance)
+                    max_distance = distance;
+            }
+        }
+        log_info("    moved %d cells, %d unplaced (after %s)\n", moved_cells, unplaced_cells, point);
+        if (moved_cells > 0) {
+            log_info("       average distance %f\n", (distance_sum / moved_cells));
+            log_info("       maximum distance %f\n", max_distance);
+        }
+    }
+
     bool legalise()
     {
         log_info("Legalising design..\n");
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            if (!ctx->getBelGlobalBuf(ci->bel) && cell.second->type == ctx->id("ICESTORM_LC")) {
+                originalPositions[cell.first] = ctx->getBelLocation(ci->bel);
+            }
+        }
         init_logic_cells();
         bool legalised_carries = legalise_carries();
         if (!legalised_carries && !ctx->force)
             return false;
+        print_stats("carry legalisation");
         legalise_others();
+        print_stats("misc. cell legalisation");
         legalise_logic_tiles();
+        print_stats("logic cell legalisation");
         bool replaced_cells = replace_cells();
+        print_stats("cell replacement");
+
         ctx->assignArchInfo();
+
+
+
         return legalised_carries && replaced_cells;
     }
 
@@ -501,6 +542,7 @@ class PlacementLegaliser
     Context *ctx;
     std::unordered_set<IdString> rippedCells;
     std::unordered_set<IdString> createdCells;
+    std::unordered_map<IdString, Loc> originalPositions;
     // Go from X and Y position to logic cells, setting occupied to true if a Bel is unavailable
     std::vector<std::vector<std::vector<std::pair<BelId, bool>>>> logic_bels;
 };