Merge remote-tracking branch 'origin/master' into chipdbng

8 files changed, 122 insertions, 21 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index c02add1c..492ed846 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -18,11 +18,12 @@
  */
 
 #include "arch_place.h"
+#include "cells.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static const NetInfo *
-get_net_or_nullptr(const CellInfo *cell, const IdString port)
+static const NetInfo *get_net_or_nullptr(const CellInfo *cell,
+                                         const IdString port)
 {
     auto found = cell->ports.find(port);
     if (found != cell->ports.end())
@@ -45,9 +46,12 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
                 clk = get_net_or_nullptr(cell, "CLK");
                 sr = get_net_or_nullptr(cell, "SR");
 
-                locals.insert(cen);
-                locals.insert(clk);
-                locals.insert(sr);
+                if (!is_global_net(cen))
+                    locals.insert(cen);
+                if (!is_global_net(clk))
+                    locals.insert(clk);
+                if (!is_global_net(sr))
+                    locals.insert(sr);
 
                 if (std::stoi(cell->params.at("NEG_CLK"))) {
                     dffs_neg = true;
@@ -93,7 +97,8 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
 
         cells.push_back(cell);
         return logicCellsCompatible(cells);
-
+    } else if (cell->type == "SB_IO") {
+        return design->chip.getBelPackagePin(bel) != "";
     } else {
         // TODO: IO cell clock checks
         return true;
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 7952a8a1..ba4a0e8d 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -67,6 +67,28 @@ void set_config(const TileInfoPOD &ti,
     }
 }
 
+int get_param_or_def(const CellInfo *cell, const std::string &param,
+                     int defval = 0)
+{
+    auto found = cell->params.find(param);
+    if (found != cell->params.end())
+        return std::stoi(found->second);
+    else
+        return defval;
+}
+
+std::string get_param_str_or_def(const CellInfo *cell, const std::string &param,
+                                 std::string defval = "")
+{
+    auto found = cell->params.find(param);
+    if (found != cell->params.end())
+        return found->second;
+    else
+        return defval;
+}
+
+char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
+
 void write_asc(const Design &design, std::ostream &out)
 {
     const Chip &chip = design.chip;
@@ -134,12 +156,12 @@ void write_asc(const Design &design, std::ostream &out)
         int x = beli.x, y = beli.y, z = beli.z;
         if (cell.second->type == "ICESTORM_LC") {
             TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
-            unsigned lut_init = std::stoi(cell.second->params["LUT_INIT"]);
-            bool neg_clk = std::stoi(cell.second->params["NEG_CLK"]);
-            bool dff_enable = std::stoi(cell.second->params["DFF_ENABLE"]);
-            bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]);
-            bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]);
-            bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]);
+            unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT");
+            bool neg_clk = get_param_or_def(cell.second, "NEG_CLK");
+            bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE");
+            bool async_sr = get_param_or_def(cell.second, "ASYNC_SR");
+            bool set_noreset = get_param_or_def(cell.second, "SET_NORESET");
+            bool carry_enable = get_param_or_def(cell.second, "CARRY_ENABLE");
             std::vector<bool> lc(20, false);
             // From arachne-pnr
             static std::vector<int> lut_perm = {
@@ -160,9 +182,9 @@ void write_asc(const Design &design, std::ostream &out)
             set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
         } else if (cell.second->type == "SB_IO") {
             TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-            unsigned pin_type = std::stoi(cell.second->params["PIN_TYPE"]);
-            bool neg_trigger = std::stoi(cell.second->params["NEG_TRIGGER"]);
-            bool pullup = std::stoi(cell.second->params["PULLUP"]);
+            unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE");
+            bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER");
+            bool pullup = get_param_or_def(cell.second, "PULLUP");
             for (int i = 0; i < 6; i++) {
                 bool val = (pin_type >> i) & 0x01;
                 set_config(ti, config.at(y).at(x),
@@ -198,11 +220,37 @@ void write_asc(const Design &design, std::ostream &out)
             }
         } else if (cell.second->type == "SB_GB") {
             // no cell config bits
+        } else if (cell.second->type == "ICESTORM_RAM") {
+            const BelInfoPOD &beli = ci.bel_data[bel.index];
+            int x = beli.x, y = beli.y;
+            const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
+            const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB];
+            if (!(chip.args.type == ChipArgs::LP1K ||
+                  chip.args.type == ChipArgs::HX1K)) {
+                set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp",
+                           true);
+            }
+            bool negclk_r = get_param_or_def(cell.second, "NEG_CLK_R");
+            bool negclk_w = get_param_or_def(cell.second, "NEG_CLK_W");
+            int write_mode = get_param_or_def(cell.second, "WRITE_MODE");
+            int read_mode = get_param_or_def(cell.second, "READ_MODE");
+            set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
+            set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
+
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0",
+                       write_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1",
+                       write_mode & 0x2);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2",
+                       read_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3",
+                       read_mode & 0x2);
+
         } else {
             assert(false);
         }
     }
-    // Set config bits in unused IO
+    // Set config bits in unused IO and RAM
     for (auto bel : chip.getBels()) {
         if (chip.bel_to_cell[bel.index] == IdString() &&
             chip.getBelType(bel) == TYPE_SB_IO) {
@@ -221,6 +269,15 @@ void write_asc(const Design &design, std::ostream &out)
                                "IoCtrl.REN_" + std::to_string(iez), false);
                 }
             }
+        } else if (chip.bel_to_cell[bel.index] == IdString() &&
+                   chip.getBelType(bel) == TYPE_ICESTORM_RAM) {
+            const BelInfoPOD &beli = ci.bel_data[bel.index];
+            int x = beli.x, y = beli.y;
+            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
+            if ((chip.args.type == ChipArgs::LP1K ||
+                 chip.args.type == ChipArgs::HX1K)) {
+                set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
+            }
         }
     }
 
@@ -312,6 +369,35 @@ void write_asc(const Design &design, std::ostream &out)
             out << std::endl;
         }
     }
+
+    // Write RAM init data
+    for (auto cell : design.cells) {
+        if (cell.second->bel != BelId()) {
+            if (cell.second->type == "ICESTORM_RAM") {
+                const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
+                int x = beli.x, y = beli.y;
+                out << ".ram_data " << x << " " << y << std::endl;
+                for (int w = 0; w < 16; w++) {
+                    std::vector<bool> bits(256);
+                    std::string init = get_param_str_or_def(
+                            cell.second,
+                            std::string("INIT_") + get_hexdigit(w));
+                    assert(init != "");
+                    for (int i = 0; i < init.size(); i++) {
+                        bool val = (init.at((init.size() - 1) - i) == '1');
+                        bits.at(i) = val;
+                    }
+                    for (int i = bits.size()-4; i >= 0; i -= 4) {
+                        int c = bits.at(i) + (bits.at(i + 1) << 1) +
+                                (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
+                        out << char(std::tolower(get_hexdigit(c)));
+                    }
+                    out << std::endl;
+                }
+                out << std::endl;
+            }
+        }
+    }
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/ice40/cells.cc b/ice40/cells.cc
index b7a02790..61b24ce3 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -190,7 +190,7 @@ void nxio_to_sb(CellInfo *nxio, CellInfo *sbio)
     }
 }
 
-bool is_global_net(NetInfo *net)
+bool is_global_net(const NetInfo *net)
 {
     return bool(net_driven_by(net, is_gbuf, "GLOBAL_BUFFER_OUTPUT"));
 }
diff --git a/ice40/cells.h b/ice40/cells.h
index e5b4fa9c..a2fa4c16 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -75,7 +75,7 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
 void nxio_to_sb(CellInfo *nxio, CellInfo *sbio);
 
 // Return true if a net is a global net
-bool is_global_net(NetInfo *net);
+bool is_global_net(const NetInfo *net);
 
 NEXTPNR_NAMESPACE_END
 
diff --git a/ice40/chip.cc b/ice40/chip.cc
index db293f43..1255dfc8 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -273,6 +273,15 @@ BelId Chip::getPackagePinBel(const std::string &pin) const
     return BelId();
 }
 
+std::string Chip::getBelPackagePin(BelId bel) const
+{
+    for (int i = 0; i < package_info->num_pins; i++) {
+        if (package_info->pins[i].bel_index == bel.index) {
+            return std::string(package_info->pins[i].name);
+        }
+    }
+    return "";
+}
 // -----------------------------------------------------------------------
 
 bool Chip::estimatePosition(BelId bel, int &x, int &y) const
diff --git a/ice40/chip.h b/ice40/chip.h
index 7460d3b2..5eeca5e9 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -713,6 +713,7 @@ struct Chip
     }
 
     BelId getPackagePinBel(const std::string &pin) const;
+    std::string getBelPackagePin(BelId bel) const;
 
     // -------------------------------------------------
 
diff --git a/ice40/main.cc b/ice40/main.cc
index d4177fb1..fea53631 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -222,7 +222,7 @@ int main(int argc, char *argv[])
 
         pack_design(&design);
         if (!vm.count("pack-only")) {
-            place_design(&design);
+            place_design_sa(&design);
             route_design(&design, verbose);
         }
     }
diff --git a/ice40/pack.cc b/ice40/pack.cc
index f4c024da..e045c05c 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -129,8 +129,8 @@ static void pack_ram(Design *design)
                                                ci->name.str() + "_RAM");
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
-            packed->params["READ_MODE"] = ci->params.at("READ_MODE");
-            packed->params["WRITE_MODE"] = ci->params.at("WRITE_MODE");
+            for (auto param : ci->params)
+                packed->params[param.first] = param.second;
             packed->params["NEG_CLK_W"] =
                     std::to_string(ci->type == "SB_RAM40_4KNW" ||
                                    ci->type == "SB_RAM40_4KNRNW");