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author | Miodrag Milanovic <mmicko@gmail.com> | 2018-07-03 08:52:19 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2018-07-03 08:53:44 +0200 |
commit | 1cf82930191d6498fc14e1854472f0d955a4c4ea (patch) | |
tree | 58edfdc7fc506ab46591beac8e74ba9dd8c5b08f /ice40 | |
parent | fe1ad5b086c46b82aa72cb0f9625ebdf941e50f9 (diff) | |
download | nextpnr-1cf82930191d6498fc14e1854472f0d955a4c4ea.tar.gz nextpnr-1cf82930191d6498fc14e1854472f0d955a4c4ea.tar.bz2 nextpnr-1cf82930191d6498fc14e1854472f0d955a4c4ea.zip |
Fixed macros and includes for MSVC
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/arch.h | 42 | ||||
-rw-r--r-- | ice40/bitstream.cc | 1 | ||||
-rw-r--r-- | ice40/pack.cc | 1 |
3 files changed, 30 insertions, 14 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 9ed30f93..207e885c 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -43,12 +43,14 @@ template <typename T> struct RelPtr const T *operator->() const { return get(); } }; +NPNR_PACKED_STRUCT( struct BelWirePOD { int32_t wire_index; PortPin port; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct BelInfoPOD { RelPtr<char> name; @@ -57,14 +59,16 @@ struct BelInfoPOD RelPtr<BelWirePOD> bel_wires; int8_t x, y, z; int8_t padding_0; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct BelPortPOD { int32_t bel_index; PortPin port; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct PipInfoPOD { int32_t src, dst; @@ -72,8 +76,9 @@ struct PipInfoPOD int8_t x, y; int16_t switch_mask; int32_t switch_index; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct WireInfoPOD { RelPtr<char> name; @@ -87,20 +92,22 @@ struct WireInfoPOD int8_t x, y; WireType type; int8_t padding_0; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct PackagePinPOD { RelPtr<char> name; int32_t bel_index; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct PackageInfoPOD { RelPtr<char> name; int32_t num_pins; RelPtr<PackagePinPOD> pins; -} __attribute__((packed)); +}); enum TileType : uint32_t { @@ -116,48 +123,55 @@ enum TileType : uint32_t TILE_IPCON = 9 }; +NPNR_PACKED_STRUCT( struct ConfigBitPOD { int8_t row, col; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct ConfigEntryPOD { RelPtr<char> name; int32_t num_bits; RelPtr<ConfigBitPOD> bits; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct TileInfoPOD { int8_t cols, rows; int16_t num_config_entries; RelPtr<ConfigEntryPOD> entries; -} __attribute__((packed)); +}); static const int max_switch_bits = 5; +NPNR_PACKED_STRUCT( struct SwitchInfoPOD { int32_t num_bits; int8_t x, y; ConfigBitPOD cbits[max_switch_bits]; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct IerenInfoPOD { int8_t iox, ioy, ioz; int8_t ierx, iery, ierz; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct BitstreamInfoPOD { int32_t num_switches, num_ierens; RelPtr<TileInfoPOD> tiles_nonrouting; RelPtr<SwitchInfoPOD> switches; RelPtr<IerenInfoPOD> ierens; -} __attribute__((packed)); +}); +NPNR_PACKED_STRUCT( struct ChipInfoPOD { int32_t width, height; @@ -169,7 +183,7 @@ struct ChipInfoPOD RelPtr<TileType> tile_grid; RelPtr<BitstreamInfoPOD> bits_info; RelPtr<PackageInfoPOD> packages_data; -} __attribute__((packed)); +}); extern const char chipdb_blob_384[]; extern const char chipdb_blob_1k[]; diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 0b6e0d35..c739d3c9 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -18,6 +18,7 @@ * */ #include "bitstream.h" +#include <cctype> #include <vector> #include "log.h" diff --git a/ice40/pack.cc b/ice40/pack.cc index 2484aa53..d1be4a29 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -20,6 +20,7 @@ #include "pack.h" #include <algorithm> +#include <iterator> #include <unordered_set> #include "cells.h" #include "design_utils.h" |