Merge branch 'master' into 'master'

Master

See merge request eddiehung/nextpnr!7

7 files changed, 212 insertions, 156 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index e9a7d2b6..65b21afd 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -19,13 +19,13 @@
 
 #include <algorithm>
 #include <cmath>
+#include "cells.h"
 #include "gfx.h"
 #include "log.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "router1.h"
 #include "util.h"
-#include "cells.h"
 NEXTPNR_NAMESPACE_BEGIN
 
 // -----------------------------------------------------------------------
@@ -279,17 +279,11 @@ BelRange Arch::getBelsByTile(int x, int y) const
     // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used
     BelRange br;
 
-    Loc loc;
-    loc.x = x;
-    loc.y = y;
-    loc.z = 0;
-
-    br.b.cursor = Arch::getBelByLocation(loc).index;
+    br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
     br.e.cursor = br.b.cursor;
 
     if (br.e.cursor != -1) {
-        while (br.e.cursor < chip_info->num_bels &&
-               chip_info->bel_data[br.e.cursor].x == x &&
+        while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
                chip_info->bel_data[br.e.cursor].y == y)
             br.e.cursor++;
     }
@@ -314,7 +308,21 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
     return br;
 }
 
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
+PortType Arch::getBelPinType(BelId bel, PortPin pin) const
+{
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        if (bel_wires[i].port == pin)
+            return PortType(bel_wires[i].type);
+
+    return PORT_INOUT;
+}
+
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
 {
     WireId ret;
 
@@ -332,6 +340,21 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
     return ret;
 }
 
+std::vector<PortPin> Arch::getBelPins(BelId bel) const
+{
+    std::vector<PortPin> ret;
+
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        ret.push_back(bel_wires[i].port);
+
+    return ret;
+}
+
 // -----------------------------------------------------------------------
 
 WireId Arch::getWireByName(IdString name) const
@@ -525,9 +548,9 @@ DecalXY Arch::getWireDecal(WireId wire) const
 DecalXY Arch::getPipDecal(PipId pip) const
 {
     DecalXY decalxy;
-    // decalxy.decal.type = DecalId::TYPE_PIP;
-    // decalxy.decal.index = pip.index;
-    // decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
+    decalxy.decal.type = DecalId::TYPE_PIP;
+    decalxy.decal.index = pip.index;
+    decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
     return decalxy;
 };
 
diff --git a/ice40/arch.h b/ice40/arch.h
index 21169298..d4d71cfc 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -46,6 +46,7 @@ template <typename T> struct RelPtr
 NPNR_PACKED_STRUCT(struct BelWirePOD {
     int32_t wire_index;
     PortPin port;
+    int32_t type;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
@@ -86,6 +87,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     BelPortPOD bel_uphill;
     RelPtr<BelPortPOD> bels_downhill;
 
+    int32_t num_bel_pins;
+    RelPtr<BelPortPOD> bel_pins;
+
     int32_t num_segments;
     RelPtr<WireSegmentPOD> segments;
 
@@ -373,6 +377,12 @@ struct Arch : BaseCtx
 
     // -------------------------------------------------
 
+    int getGridDimX() const { return 34; }
+    int getGridDimY() const { return 34; }
+    int getTileDimZ(int, int) const { return 8; }
+
+    // -------------------------------------------------
+
     BelId getBelByName(IdString name) const;
 
     IdString getBelName(BelId bel) const
@@ -390,6 +400,7 @@ struct Arch : BaseCtx
         bel_to_cell[bel.index] = cell;
         cells[cell]->bel = bel;
         cells[cell]->belStrength = strength;
+        refreshUiBel(bel);
     }
 
     void unbindBel(BelId bel)
@@ -399,6 +410,7 @@ struct Arch : BaseCtx
         cells[bel_to_cell[bel.index]]->bel = BelId();
         cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE;
         bel_to_cell[bel.index] = IdString();
+        refreshUiBel(bel);
     }
 
     bool checkBelAvail(BelId bel) const
@@ -427,20 +439,6 @@ struct Arch : BaseCtx
         return range;
     }
 
-    BelRange getBelsByType(BelType type) const
-    {
-        BelRange range;
-// FIXME
-#if 0
-		if (type == "TYPE_A") {
-			range.b.cursor = bels_type_a_begin;
-			range.e.cursor = bels_type_a_end;
-		}
-		...
-#endif
-        return range;
-    }
-
     Loc getBelLocation(BelId bel) const
     {
         Loc loc;
@@ -453,10 +451,7 @@ struct Arch : BaseCtx
     BelId getBelByLocation(Loc loc) const;
     BelRange getBelsByTile(int x, int y) const;
 
-    bool getBelGlobalBuf(BelId bel) const
-    {
-        return chip_info->bel_data[bel.index].type == TYPE_SB_GB;
-    }
+    bool getBelGlobalBuf(BelId bel) const { return chip_info->bel_data[bel.index].type == TYPE_SB_GB; }
 
     BelRange getBelsAtSameTile(BelId bel) const NPNR_DEPRECATED;
 
@@ -466,29 +461,9 @@ struct Arch : BaseCtx
         return chip_info->bel_data[bel.index].type;
     }
 
-    WireId getWireBelPin(BelId bel, PortPin pin) const;
-
-    BelPin getBelPinUphill(WireId wire) const
-    {
-        BelPin ret;
-        NPNR_ASSERT(wire != WireId());
-
-        if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
-            ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
-            ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
-        }
-
-        return ret;
-    }
-
-    BelPinRange getBelPinsDownhill(WireId wire) const
-    {
-        BelPinRange range;
-        NPNR_ASSERT(wire != WireId());
-        range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
-        range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
-        return range;
-    }
+    WireId getBelPinWire(BelId bel, PortPin pin) const;
+    PortType getBelPinType(BelId bel, PortPin pin) const;
+    std::vector<PortPin> getBelPins(BelId bel) const;
 
     // -------------------------------------------------
 
@@ -509,6 +484,7 @@ struct Arch : BaseCtx
         wire_to_net[wire.index] = net;
         nets[net]->wires[wire].pip = PipId();
         nets[net]->wires[wire].strength = strength;
+        refreshUiWire(wire);
     }
 
     void unbindWire(WireId wire)
@@ -528,6 +504,7 @@ struct Arch : BaseCtx
 
         net_wires.erase(it);
         wire_to_net[wire.index] = IdString();
+        refreshUiWire(wire);
     }
 
     bool checkWireAvail(WireId wire) const
@@ -554,6 +531,15 @@ struct Arch : BaseCtx
         return delay;
     }
 
+    BelPinRange getWireBelPins(WireId wire) const
+    {
+        BelPinRange range;
+        NPNR_ASSERT(wire != WireId());
+        range.b.ptr = chip_info->wire_data[wire.index].bel_pins.get();
+        range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bel_pins;
+        return range;
+    }
+
     WireRange getWires() const
     {
         WireRange range;
@@ -581,6 +567,8 @@ struct Arch : BaseCtx
         wire_to_net[dst.index] = net;
         nets[net]->wires[dst].pip = pip;
         nets[net]->wires[dst].strength = strength;
+        refreshUiPip(pip);
+        refreshUiWire(dst);
     }
 
     void unbindPip(PipId pip)
@@ -597,6 +585,8 @@ struct Arch : BaseCtx
 
         pip_to_net[pip.index] = IdString();
         switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
+        refreshUiPip(pip);
+        refreshUiWire(dst);
     }
 
     bool checkPipAvail(PipId pip) const
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 116ab7d3..cf1276a7 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -110,7 +110,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
     } else if (cell->type == id_sb_gb) {
         NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
         const NetInfo *net = cell->ports.at(id_glb_buf_out).net;
-        IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
+        IdString glb_net = getWireName(getBelPinWire(bel, PIN_GLOBAL_BUFFER_OUTPUT));
         int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
         if (net->is_reset && net->is_enable)
             return false;
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index fd5109b4..246d0f57 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -82,12 +82,10 @@ void arch_wrap_python()
     fn_wrapper_1a<Context, decltype(&Context::getBelsAtSameTile), &Context::getBelsAtSameTile, wrap_context<BelRange>,
                   conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelsAtSameTile");
 
-    fn_wrapper_2a<Context, decltype(&Context::getWireBelPin), &Context::getWireBelPin, conv_to_str<WireId>,
-                  conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getWireBelPin");
-    fn_wrapper_1a<Context, decltype(&Context::getBelPinUphill), &Context::getBelPinUphill, wrap_context<BelPin>,
-                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinUphill");
-    fn_wrapper_1a<Context, decltype(&Context::getBelPinsDownhill), &Context::getBelPinsDownhill,
-                  wrap_context<BelPinRange>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinsDownhill");
+    fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
+                  conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
+    fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>,
+                  conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins");
 
     fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
                   conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 7fd3f8ac..9ac8e857 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -319,8 +319,8 @@ void write_asc(const Context *ctx, std::ostream &out)
             NPNR_ASSERT(iez != -1);

 

             bool input_en = false;

-            if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||

-                (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {

+            if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) ||

+                (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) {

                 input_en = true;

             }

 

@@ -482,8 +482,9 @@ void write_asc(const Context *ctx, std::ostream &out)
                             set_config(ti, config.at(y).at(x),

                                        "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);

                         else

-                            set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) +

-                                                                       "_LC0" + std::to_string(lc_idx) + "_inmux02_5",

+                            set_config(ti, config.at(y).at(x),

+                                       "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +

+                                               std::to_string(lc_idx) + "_inmux02_5",

                                        true);

                     }

                 }

@@ -717,42 +718,44 @@ bool read_asc(Context *ctx, std::istream &in)
             for (auto w : net.second->wires) {

                 if (w.second.pip == PipId()) {

                     WireId wire = w.first;

-                    BelPin belpin = ctx->getBelPinUphill(wire);

-                    if (ctx->checkBelAvail(belpin.bel)) {

-                        if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) {

-                            std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));

-                            IdString name = created->name;

-                            ctx->cells[name] = std::move(created);

-                            ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

-                            // TODO: Add port mapping to nets

-                        }

-                        if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) {

-                            std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));

-                            IdString name = created->name;

-                            ctx->cells[name] = std::move(created);

-                            ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

-                            // TODO: Add port mapping to nets

-                        }

-                        if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) {

-                            std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));

-                            IdString name = created->name;

-                            ctx->cells[name] = std::move(created);

-                            ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

-                            // TODO: Add port mapping to nets

-                        }

-                        if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) {

-                            std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));

-                            IdString name = created->name;

-                            ctx->cells[name] = std::move(created);

-                            ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

-                            // TODO: Add port mapping to nets

-                        }

-                        if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) {

-                            std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));

-                            IdString name = created->name;

-                            ctx->cells[name] = std::move(created);

-                            ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

-                            // TODO: Add port mapping to nets

+                    for (auto belpin : ctx->getWireBelPins(wire)) {

+

+                        if (ctx->checkBelAvail(belpin.bel)) {

+                            if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) {

+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));

+                                IdString name = created->name;

+                                ctx->cells[name] = std::move(created);

+                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                // TODO: Add port mapping to nets

+                            }

+                            if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) {

+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));

+                                IdString name = created->name;

+                                ctx->cells[name] = std::move(created);

+                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                // TODO: Add port mapping to nets

+                            }

+                            if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) {

+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));

+                                IdString name = created->name;

+                                ctx->cells[name] = std::move(created);

+                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                // TODO: Add port mapping to nets

+                            }

+                            if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) {

+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));

+                                IdString name = created->name;

+                                ctx->cells[name] = std::move(created);

+                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                // TODO: Add port mapping to nets

+                            }

+                            if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) {

+                                std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));

+                                IdString name = created->name;

+                                ctx->cells[name] = std::move(created);

+                                ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);

+                                // TODO: Add port mapping to nets

+                            }

                         }

                     }

                 }

@@ -762,7 +765,7 @@ bool read_asc(Context *ctx, std::istream &in)
             if (cell.second->bel != BelId()) {

                 for (auto &port : cell.second->ports) {

                     PortPin pin = ctx->portPinFromId(port.first);

-                    WireId wire = ctx->getWireBelPin(cell.second->bel, pin);

+                    WireId wire = ctx->getBelPinWire(cell.second->bel, pin);

                     if (wire != WireId()) {

                         IdString name = ctx->getBoundWireNet(wire);

                         if (name != IdString()) {

diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 329fef56..0e8e3ba7 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -43,6 +43,7 @@ packages = list()
 
 wire_uphill_belport = dict()
 wire_downhill_belports = dict()
+wire_belports = dict()
 
 wire_names = dict()
 wire_names_r = dict()
@@ -372,8 +373,12 @@ with open(args.filename, "r") as f:
         if line[0] == ".extra_cell":
             if len(line) >= 5:
                 mode = ("extra_cell", (line[4], int(line[1]), int(line[2]), int(line[3])))
-            else:
+            elif line[3] == "WARMBOOT":
+                mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 0))
+            elif line[3] == "PLL":
                 mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 3))
+            else:
+                assert 0
             extra_cells[mode[1]] = []
             continue
 
@@ -449,12 +454,18 @@ def add_bel_input(bel, wire, port):
     if wire not in wire_downhill_belports:
         wire_downhill_belports[wire] = set()
     wire_downhill_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port))
+    if wire not in wire_belports:
+        wire_belports[wire] = set()
+    wire_belports[wire].add((bel, port))
+    bel_wires[bel].append((wire, port, 0))
 
 def add_bel_output(bel, wire, port):
     assert wire not in wire_uphill_belport
     wire_uphill_belport[wire] = (bel, port)
-    bel_wires[bel].append((wire, port))
+    if wire not in wire_belports:
+        wire_belports[wire] = set()
+    wire_belports[wire].add((bel, port))
+    bel_wires[bel].append((wire, port, 1))
 
 def add_bel_lc(x, y, z):
     bel = len(bel_name)
@@ -557,11 +568,14 @@ def add_bel_ram(x, y):
     add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE")
     add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE")
 
-def add_bel_gb(x, y, g):
+def add_bel_gb(xy, x, y, g):
+    if xy[0] != x or xy[1] != y:
+        return
+
     bel = len(bel_name)
     bel_name.append("X%d/Y%d/gb" % (x, y))
     bel_type.append("SB_GB")
-    bel_pos.append((x, y, 0))
+    bel_pos.append((x, y, 2))
     bel_wires.append(list())
 
     add_bel_input(bel, wire_names[(x, y, "fabout")], "USER_SIGNAL_TO_GLOBAL_BUFFER")
@@ -598,51 +612,58 @@ for tile_xy, tile_type in sorted(tiles.items()):
     if tile_type == "logic":
         for i in range(8):
             add_bel_lc(tile_xy[0], tile_xy[1], i)
+
     if tile_type == "io":
         for i in range(2):
             add_bel_io(tile_xy[0], tile_xy[1], i)
+
+        if dev_name == "1k":
+            add_bel_gb(tile_xy,  7,  0, 0)
+            add_bel_gb(tile_xy,  7, 17, 1)
+            add_bel_gb(tile_xy, 13,  9, 2)
+            add_bel_gb(tile_xy,  0,  9, 3)
+            add_bel_gb(tile_xy,  6, 17, 4)
+            add_bel_gb(tile_xy,  6,  0, 5)
+            add_bel_gb(tile_xy,  0,  8, 6)
+            add_bel_gb(tile_xy, 13,  8, 7)
+        elif dev_name == "5k":
+            add_bel_gb(tile_xy, 13,  0, 0)
+            add_bel_gb(tile_xy, 13, 31, 1)
+            add_bel_gb(tile_xy, 19, 31, 2)
+            add_bel_gb(tile_xy,  6, 31, 3)
+            add_bel_gb(tile_xy, 12, 31, 4)
+            add_bel_gb(tile_xy, 12,  0, 5)
+            add_bel_gb(tile_xy,  6,  0, 6)
+            add_bel_gb(tile_xy, 19,  0, 7)
+        elif dev_name == "8k":
+            add_bel_gb(tile_xy, 33, 16,  7)
+            add_bel_gb(tile_xy,  0, 16,  6)
+            add_bel_gb(tile_xy, 17, 33,  1)
+            add_bel_gb(tile_xy, 17,  0,  0)
+            add_bel_gb(tile_xy,  0, 17,  3)
+            add_bel_gb(tile_xy, 33, 17,  2)
+            add_bel_gb(tile_xy, 16,  0,  5)
+            add_bel_gb(tile_xy, 16, 33,  4)
+        elif dev_name == "384":
+            add_bel_gb(tile_xy,  7,  4,  7)
+            add_bel_gb(tile_xy,  0,  4,  6)
+            add_bel_gb(tile_xy,  4,  9,  1)
+            add_bel_gb(tile_xy,  4,  0,  0)
+            add_bel_gb(tile_xy,  0,  5,  3)
+            add_bel_gb(tile_xy,  7,  5,  2)
+            add_bel_gb(tile_xy,  3,  0,  5)
+            add_bel_gb(tile_xy,  3,  9,  4)
+
     if tile_type == "ramb":
         add_bel_ram(tile_xy[0], tile_xy[1])
 
-if dev_name == "1k":
-    add_bel_gb( 7,  0, 0)
-    add_bel_gb( 7, 17, 1)
-    add_bel_gb(13,  9, 2)
-    add_bel_gb( 0,  9, 3)
-    add_bel_gb( 6, 17, 4)
-    add_bel_gb( 6,  0, 5)
-    add_bel_gb( 0,  8, 6)
-    add_bel_gb(13,  8, 7)
-elif dev_name == "5k":
-    add_bel_gb(13,  0, 0)
-    add_bel_gb(13, 31, 1)
-    add_bel_gb(19, 31, 2)
-    add_bel_gb( 6, 31, 3)
-    add_bel_gb(12, 31, 4)
-    add_bel_gb(12,  0, 5)
-    add_bel_gb( 6,  0, 6)
-    add_bel_gb(19,  0, 7)
-elif dev_name == "8k":
-    add_bel_gb(33, 16,  7)
-    add_bel_gb( 0, 16,  6)
-    add_bel_gb(17, 33,  1)
-    add_bel_gb(17,  0,  0)
-    add_bel_gb( 0, 17,  3)
-    add_bel_gb(33, 17,  2)
-    add_bel_gb(16,  0,  5)
-    add_bel_gb(16, 33,  4)
-elif dev_name == "384":
-    add_bel_gb( 7,  4,  7)
-    add_bel_gb( 0,  4,  6)
-    add_bel_gb( 4,  9,  1)
-    add_bel_gb( 4,  0,  0)
-    add_bel_gb( 0,  5,  3)
-    add_bel_gb( 7,  5,  2)
-    add_bel_gb( 3,  0,  5)
-    add_bel_gb( 3,  9,  4)
+    for ec in sorted(extra_cells.keys()):
+        if ec[1] == tile_xy[0] and ec[2] == tile_xy[1]:
+            add_bel_ec(ec)
 
 for ec in sorted(extra_cells.keys()):
-    add_bel_ec(ec)
+    if ec[1] == 0 and ec[2] == 0:
+        add_bel_ec(ec)
 
 class BinaryBlobAssembler:
     def __init__(self, cname, endianness, nodebug = False):
@@ -913,6 +934,7 @@ for bel in range(len(bel_name)):
     for i in range(len(bel_wires[bel])):
         bba.u32(bel_wires[bel][i][0], "wire_index")
         bba.u32(portpins[bel_wires[bel][i][1]], "port")
+        bba.u32(bel_wires[bel][i][2], "type")
         index += 1
 
 bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
@@ -988,6 +1010,15 @@ for wire in range(num_wires):
     else:
         num_bels_downhill = 0
 
+    if wire in wire_belports:
+        num_bel_pins = len(wire_belports[wire])
+        bba.l("wire%d_bels" % wire, "BelPortPOD")
+        for belport in sorted(wire_belports[wire]):
+            bba.u32(belport[0], "bel_index")
+            bba.u32(portpins[belport[1]], "port")
+    else:
+        num_bel_pins = 0
+
     info = dict()
     info["name"] = "X%d/Y%d/%s" % wire_names_r[wire]
 
@@ -1000,6 +1031,9 @@ for wire in range(num_wires):
     info["num_bels_downhill"] = num_bels_downhill
     info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None
 
+    info["num_bel_pins"] = num_bel_pins
+    info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
+
     if wire in wire_uphill_belport:
         info["uphill_bel"] = wire_uphill_belport[wire][0]
         info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]]
@@ -1085,6 +1119,8 @@ for wire, info in enumerate(wireinfo):
     bba.u32(info["uphill_bel"], "bel_uphill.bel_index")
     bba.u32(info["uphill_pin"], "bel_uphill.port")
     bba.r(info["list_bels_downhill"], "bels_downhill")
+    bba.u32(info["num_bel_pins"], "num_bel_pins")
+    bba.r(info["list_bel_pins"], "bel_pins")
     bba.u32(len(wire_segments[wire]), "num_segments")
     if len(wire_segments[wire]):
         bba.r("wire_segments_%d" % wire, "segments")
diff --git a/ice40/main.cc b/ice40/main.cc
index 70324a91..4de05d00 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -69,8 +69,8 @@ void svg_dump_decal(const Context *ctx, const DecalXY &decal)
 void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2)
 {
     if (vm.count(opt1) && !vm[opt1].defaulted() && vm.count(opt2) && !vm[opt2].defaulted()) {
-        std::string msg = "Conflicting options '"+ std::string(opt1) + "' and '" + std::string(opt1) + "'.";
-        log_error("%s\n",msg.c_str());
+        std::string msg = "Conflicting options '" + std::string(opt1) + "' and '" + std::string(opt1) + "'.";
+        log_error("%s\n", msg.c_str());
     }
 }
 
@@ -107,6 +107,7 @@ int main(int argc, char *argv[])
         options.add_options()("seed", po::value<int>(), "seed value for random number generator");
         options.add_options()("version,V", "show version");
         options.add_options()("tmfuzz", "run path delay estimate fuzzer");
+        options.add_options()("test", "check architecture database integrity");
 #ifdef ICE40_HX1K_ONLY
         options.add_options()("hx1k", "set device type to iCE40HX1K");
 #else
@@ -315,6 +316,9 @@ int main(int argc, char *argv[])
             std::cout << "</svg>\n";
         }
 
+        if (vm.count("test"))
+            ctx->archcheck();
+
         if (vm.count("tmfuzz")) {
             std::vector<WireId> src_wires, dst_wires;
 
@@ -322,25 +326,25 @@ int main(int argc, char *argv[])
                 src_wires.push_back(w);*/
             for (auto b : ctx->getBels()) {
                 if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
-                    src_wires.push_back(ctx->getWireBelPin(b, PIN_O));
+                    src_wires.push_back(ctx->getBelPinWire(b, PIN_O));
                 }
                 if (ctx->getBelType(b) == TYPE_SB_IO) {
-                    src_wires.push_back(ctx->getWireBelPin(b, PIN_D_IN_0));
+                    src_wires.push_back(ctx->getBelPinWire(b, PIN_D_IN_0));
                 }
             }
 
             for (auto b : ctx->getBels()) {
                 if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_I0));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_I1));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_I2));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_I3));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_CEN));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_CIN));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_I0));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_I1));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_I2));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_I3));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_CEN));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_CIN));
                 }
                 if (ctx->getBelType(b) == TYPE_SB_IO) {
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_D_OUT_0));
-                    dst_wires.push_back(ctx->getWireBelPin(b, PIN_OUTPUT_ENABLE));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_D_OUT_0));
+                    dst_wires.push_back(ctx->getBelPinWire(b, PIN_OUTPUT_ENABLE));
                 }
             }
 
@@ -360,8 +364,10 @@ int main(int argc, char *argv[])
                        ctx->chip_info->wire_data[dst.index].type);
             }
         }
+
         if (vm.count("freq"))
             ctx->target_freq = vm["freq"].as<double>() * 1e6;
+
         ctx->timing_driven = true;
         if (vm.count("no-tmdriv"))
             ctx->timing_driven = false;