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authorDavid Shah <davey1576@gmail.com>2018-06-26 15:06:59 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-26 15:06:59 +0200
commit6f12f2b7e8c58a0b14c6f1f3df2112b8860a6e4f (patch)
treeb8617ab8460f4b59c8d074660b6572fb4a84ba26 /ice40/carry_tests
parent29df577f14c8e6f870c4dfbd633effc664219252 (diff)
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Working on debugging the carry legaliser
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/carry_tests')
-rwxr-xr-xice40/carry_tests/test.sh22
1 files changed, 11 insertions, 11 deletions
diff --git a/ice40/carry_tests/test.sh b/ice40/carry_tests/test.sh
index 47a9e5ef..9f6b00b2 100755
--- a/ice40/carry_tests/test.sh
+++ b/ice40/carry_tests/test.sh
@@ -2,15 +2,15 @@
set -ex
NAME=${1%.v}
yosys -p "synth_ice40 -top top; write_json ${NAME}.json" $1
-../../nextpnr-ice40 --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose
-icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
+../../nextpnr-ice40 --force --json ${NAME}.json --pcf test.pcf --asc ${NAME}.asc --verbose ../../python/dump_design.py
+#icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
-yosys -p "read_verilog +/ice40/cells_sim.v;\
- rename chip gate;\
- read_verilog $1;\
- rename top gold;\
- hierarchy;\
- proc;\
- clk2fflogic;\
- miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
- sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v
+#yosys -p "read_verilog +/ice40/cells_sim.v;\
+# rename chip gate;\
+# read_verilog $1;\
+# rename top gold;\
+# hierarchy;\
+# proc;\
+# clk2fflogic;\
+# miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
+# sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v