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authorDavid Shah <davey1576@gmail.com>2018-08-05 14:31:43 +0200
committerGitHub <noreply@github.com>2018-08-05 14:31:43 +0200
commitba97c233fb6e4502f3465a602f997cc2382f0e06 (patch)
tree3a62397aebff56e2031f3d5c6c930ead2699d641 /ice40/archdefs.h
parent8a9b3626d32e8845dc51044e0f281c0ccdb7e53a (diff)
parent287fe7e89451b952d15c7839aff9cb3db12bf807 (diff)
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Merge pull request #36 from YosysHQ/lutperm
Add LUT input permutations, improvements in ice40 timing model, improvements in router
Diffstat (limited to 'ice40/archdefs.h')
-rw-r--r--ice40/archdefs.h15
1 files changed, 3 insertions, 12 deletions
diff --git a/ice40/archdefs.h b/ice40/archdefs.h
index 9329609e..7125ba16 100644
--- a/ice40/archdefs.h
+++ b/ice40/archdefs.h
@@ -77,17 +77,6 @@ enum PortPin : int32_t
PIN_MAXIDX
};
-enum WireType : int8_t
-{
- WIRE_TYPE_NONE = 0,
- WIRE_TYPE_LOCAL = 1,
- WIRE_TYPE_GLOBAL = 2,
- WIRE_TYPE_SP4_VERT = 3,
- WIRE_TYPE_SP4_HORZ = 4,
- WIRE_TYPE_SP12_HORZ = 5,
- WIRE_TYPE_SP12_VERT = 6
-};
-
struct BelId
{
int32_t index = -1;
@@ -167,7 +156,9 @@ struct ArchCellInfo
{
struct
{
- bool dffEnable, negClk;
+ bool dffEnable;
+ bool carryEnable;
+ bool negClk;
int inputCount;
const NetInfo *clk, *cen, *sr;
} lcInfo;