Merge pull request #79 from YosysHQ/ice40lvds

ice40: Adding LVDS input support

1 files changed, 22 insertions, 1 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index c69fd34f..b436f7d7 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -34,7 +34,7 @@ bool Arch::logicCellsCompatible(const CellInfo** it, const size_t size) const
     int locals_count = 0;
 
     for (auto cell : boost::make_iterator_range(it, it+size)) {
-        NPNR_ASSERT(cell->belType == id_ICESTORM_LC);
+        NPNR_ASSERT(cell->type == id_ICESTORM_LC);
         if (cell->lcInfo.dffEnable) {
             if (!dffs_exist) {
                 dffs_exist = true;
@@ -139,6 +139,27 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
                 }
             }
         }
+        Loc ioLoc = getBelLocation(bel);
+        Loc compLoc = ioLoc;
+        compLoc.z = 1 - compLoc.z;
+
+        // Check LVDS pairing
+        if (cell->ioInfo.lvds) {
+            // Check correct z and complement location is free
+            if (ioLoc.z != 0)
+                return false;
+            BelId compBel = getBelByLocation(compLoc);
+            CellInfo *compCell = getBoundBelCell(compBel);
+            if (compCell)
+                return false;
+        } else {
+            // Check LVDS IO is not placed at complement location
+            BelId compBel = getBelByLocation(compLoc);
+            CellInfo *compCell = getBoundBelCell(compBel);
+            if (compCell && compCell->ioInfo.lvds)
+                return false;
+        }
+
         return getBelPackagePin(bel) != "";
     } else if (cell->type == id_SB_GB) {
         NPNR_ASSERT(cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net != nullptr);