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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-03 12:51:37 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-03 12:51:37 +0200 |
| commit | e673d9d2dbacab744e847a3dad71b02da05db9b8 (patch) | |
| tree | b6b7e8081c873f4416b65b6b1a2c564275e7eb42 /ice40/arch.h | |
| parent | 751a5457dcd8ce3acd9aa08591f56310c85210d4 (diff) | |
| parent | 35bc80e13057aeaad15c06f8c6bf0686328532e6 (diff) | |
| download | nextpnr-e673d9d2dbacab744e847a3dad71b02da05db9b8.tar.gz nextpnr-e673d9d2dbacab744e847a3dad71b02da05db9b8.tar.bz2 nextpnr-e673d9d2dbacab744e847a3dad71b02da05db9b8.zip | |
Merge pull request #22 from YosysHQ/routethru
Add iCE40 LUT route-through pips
Diffstat (limited to 'ice40/arch.h')
| -rw-r--r-- | ice40/arch.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index e67f2aa9..98361132 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -141,6 +141,7 @@ static const int max_switch_bits = 5; NPNR_PACKED_STRUCT(struct SwitchInfoPOD { int32_t num_bits; + int32_t bel; int8_t x, y; ConfigBitPOD cbits[max_switch_bits]; }); @@ -613,7 +614,16 @@ struct Arch : BaseCtx bool checkPipAvail(PipId pip) const { NPNR_ASSERT(pip != PipId()); - return switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString(); + int switch_idx = chip_info->pip_data[pip.index].switch_index; + + if (switches_locked[switch_idx] != IdString()) + return false; + + int bel_idx = chip_info->bits_info->switches[switch_idx].bel; + if (bel_idx >= 0 && bel_to_cell[bel_idx] != IdString()) + return false; + + return true; } IdString getBoundPipNet(PipId pip) const |