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authorDavid Shah <davey1576@gmail.com>2019-01-27 17:13:46 +0000
committerGitHub <noreply@github.com>2019-01-27 17:13:46 +0000
commit6cc1bfcb37199e0988d0f06ce34071b409ab8019 (patch)
tree158833005b2aa99c370b27253bbbf6732b92f369 /ice40/arch.h
parentb8bff6b8b595c1991e9a9e02528999abc03a3543 (diff)
parentcc53c312de168a2b44aa5ec5da436f2caebdc83e (diff)
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Merge pull request #217 from YosysHQ/timingfixes
[timing] Path related fixes
Diffstat (limited to 'ice40/arch.h')
-rw-r--r--ice40/arch.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index 10255dbe..2dd6b06c 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -841,8 +841,11 @@ struct Arch : BaseCtx
// -------------------------------------------------
// Get the delay through a cell from one port to another, returning false
- // if no path exists
+ // if no path exists. This only considers combinational delays, as required by the Arch API
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
+ // getCellDelayInternal is similar to the above, but without false path checks and including clock to out delays
+ // for internal arch use only
+ bool getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
// Get the TimingClockingInfo of a port