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author | Sergiusz Bazanski <q3k@q3k.org> | 2018-07-20 10:59:33 +0100 |
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committer | Sergiusz Bazanski <q3k@q3k.org> | 2018-07-20 10:59:33 +0100 |
commit | 55d5f8f248a00581e54b818d747d5f42ddb5f6bb (patch) | |
tree | 4f40c21efb01e6d341fd13ca8e74c1f640b483e8 /ice40/arch.h | |
parent | 0385ad1b1cc3dcd4673b3c674bc28ca12a7c7450 (diff) | |
parent | 3bad9c26cff1ba2da7f1810e5915246874780744 (diff) | |
download | nextpnr-55d5f8f248a00581e54b818d747d5f42ddb5f6bb.tar.gz nextpnr-55d5f8f248a00581e54b818d747d5f42ddb5f6bb.tar.bz2 nextpnr-55d5f8f248a00581e54b818d747d5f42ddb5f6bb.zip |
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-electric-boogaloo
Diffstat (limited to 'ice40/arch.h')
-rw-r--r-- | ice40/arch.h | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index b89a0b54..f00d7f8a 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -153,15 +153,31 @@ NPNR_PACKED_STRUCT(struct BitstreamInfoPOD { RelPtr<IerenInfoPOD> ierens; }); +NPNR_PACKED_STRUCT(struct BelConfigEntryPOD { + RelPtr<char> entry_name; + RelPtr<char> cbit_name; + int8_t x, y; + int16_t padding; +}); + +// Stores mapping between bel parameters and config bits, +// for extra cells where this mapping is non-trivial +NPNR_PACKED_STRUCT(struct BelConfigPOD { + int32_t bel_index; + int32_t num_entries; + RelPtr<BelConfigEntryPOD> entries; +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t width, height; int32_t num_bels, num_wires, num_pips; - int32_t num_switches, num_packages; + int32_t num_switches, num_belcfgs, num_packages; RelPtr<BelInfoPOD> bel_data; RelPtr<WireInfoPOD> wire_data; RelPtr<PipInfoPOD> pip_data; RelPtr<TileType> tile_grid; RelPtr<BitstreamInfoPOD> bits_info; + RelPtr<BelConfigPOD> bel_config; RelPtr<PackageInfoPOD> packages_data; }); @@ -592,7 +608,7 @@ struct Arch : BaseCtx range.e.cursor = chip_info->num_pips; return range; } - + IdString getPipName(PipId pip) const; uint32_t getPipChecksum(PipId pip) const { return pip.index; } @@ -713,6 +729,12 @@ struct Arch : BaseCtx // Helper function for above bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const; + // ------------------------------------------------- + // Assign architecure-specific arguments to nets and cells, which must be called between packing or further + // netlist modifications, and validity checks + void assignArchInfo(); + void assignCellInfo(CellInfo *cell); + IdString id_glb_buf_out; IdString id_icestorm_lc, id_sb_io, id_sb_gb; IdString id_cen, id_clk, id_sr; |